Wouldn’t need any extra MCU pins or AND gates/transistors with a wiring scheme similar to this. Just use one clock to shift all the data (3 bytes) in series and 3 latch pins (chip selects) to load what you want to appear on the parallel outputs.
Way too high, not good for decoupling/bypass … what I recommended is from the datasheet.
NPN is ideal for low side switching (you linked to an NPN transistor), PNP is ideal for high side switching.
I think if you show your full circuit, you may get some good suggestions on how to enhance it, save pins, etc.
My reasoning for not doing that must have been aiming for a ‘generic’ solution - faster, adding more registers won’t affect high-impedance period - when it really wasn’t necessary. Software engineering background isn’t doing me any favors here. I’ll do as you suggest and just cascade them all.
Oh, I had assumed that 0.01µF was just the minimum you should use. What happens when the capacitor is too large?
C1 decreases the turn on time as it acts like a short initially, hence lots of base current.
R2 discharges the base emitter capacitance at turn off time therefore decreases the turn off time.
-12v can be GND.
Why not have it act like a short all the time (remove it and R1)? Wouldn’t that improve switching times even more?
And why not also use Schottky diodes with Vf lower than the transistor’s VBE(on) to immediately drain BE capacitance when an input goes LOW, turning it off instantly? Then R2 wouldn’t be needed either.
Is there some reason not to use a TTL or CMOS AND gate?
No reason. I’d use one. I’m just trying to figure out why things are done the way they are.