AND gate using single BJT?

So I tried using a BC182 as an AND gate by connecting the 2 inputs to the base and collector. It seemed to work fine when the emitter was driving a LED, but now that I have attached it to a 595 input instead, I’m running into trouble.

I have a 100k resistor at the gate and a 100k pulldown at the emitter / 595 input (CLK pin). Vcc is 3.3V. CLK is triggering when it shouldn’t be (gate is HIGH, collector is LOW).

I assume it’s because of leakage current… is this correct? It’s given as 15nA @ 4V in the BC182 datasheet. I don’t know what IOZ is in the 595 datasheet, but I am guessing II, which is 0.1nA @ 6V, is the input current for the logic pins…

Maybe just go the usual way of making an AND gate - with two bjts.

Also check out this link here: click here
And this one too: click here

Ahh, that explains it. Glad I didn’t fry my MCU.

Hypothetically, what if I were to put a diode in series with the collector to prevent B-C current flow when B is HIGH and C is LOW?

Simple - use negative logic.

Emiter to ground, resisitors from A & B to base - with diodes if you like to prevent reverse conduction.

Collector to your “595” input, wih a suitable pull-up.

When A AND B are both LOW collector is high.

Whats a 595? please post link to data sheets.

Sorry, I meant the SN74HC595, and here's the datasheet for the BC182.

You've enlightened me once again. Why isn't this method favored over using 2 BJT's?

Glad I didn't fry my MCU.

Can't your MCU do the AND function, then have only one signal connected to the clock of the SN74HC595?
(we don't know what the 2 signals are and if they're 3.3V)

Using an NPN transistor as both an AND gate and high side switch is not, well, popular ... but first of all, have you connected a 0.01µF or 0.022µF bypass capacitor to the SN74HC595? (this is needed).

I guess you could test the single BJT transistor idea but you'll loose about 0.6V collector to emitter. Need to speed things up considerably by using a stronger signals ... try 1K in series with the base and 1K from emitter to ground. Might also need 10K pulldown resistor from the signal side of the base resistor to ground to ensure that the transistor remains off when the MCU is shut down or powering up.

This circuit only uses one transistor, but there are other components. The logic AND is essentially done by the diodes with a transistor inverter following.


Taken from here: https://electronicspani.com/diode-transistor-logic-gate/

dlloyd:
Can't your MCU do the AND function, then have only one signal connected to the clock of the SN74HC595?
(we don't know what the 2 signals are and if they're 3.3V)

Using an NPN transistor as both an AND gate and high side switch is not, well, popular ... but first of all, have you connected a 0.01µF or 0.022µF bypass capacitor to the SN74HC595? (this is needed).

I guess you could test the single BJT transistor idea but you'll loose about 0.6V collector to emitter. Need to speed things up considerably by using a stronger signals ... try 1K in series with the base and 1K from emitter to ground. Might also need 10K pulldown resistor from the signal side of the base resistor to ground to ensure that the transistor remains off when the MCU is shut down or powering up.

The reason I'm not doing the logic in software is this: I've got several SN74HC595's that need to be controlled independently, but only a couple pins to work with. Each of their clocks is (or should be, had I done it properly) attached to an AND output. Each AND has 2 inputs - an MCU pin (same one for all of them) and an output of my "chip select" SN74HC595. The "chip select" is controlled directly by the MCU. So if I want to control the 3rd SN74HC595, I set "chip select" to 0b00000100. Then SN74HC595 #3's clock will see 1 when the MCU pin is 1, but the other SN74HC595's clocks will always see 0 because the "chip select" input of their AND gates is 0.

I do have a 10µF ceramic cap across every IC. Where does the preference for low side switching come from? Would it be better to use a PNP transistor with a NAND?

I'll do as you suggest and use 1k resistors instead, with a 10k pulldown. Let's see what happens!

MrMark:
This circuit only uses one transistor, but there are other components. The logic AND is essentially done by the diodes with a transistor inverter following.


Taken from here: https://electronicspani.com/diode-transistor-logic-gate/

Interesting, thank you for posting. I understand about half... what's the purpose of C1, R1, and R2? Why -12V instead of GND?

So if I want to control the 3rd SN74HC595, I set "chip select" to 0b00000100. Then SN74HC595 #3's clock will see 1 when the MCU pin is 1, but the other SN74HC595's clocks will always see 0 because the "chip select" input of their AND gates is 0.

Wouldn't need any extra MCU pins or AND gates/transistors with a wiring scheme similar to this. Just use one clock to shift all the data (3 bytes) in series and 3 latch pins (chip selects) to load what you want to appear on the parallel outputs.

I do have a 10µF ceramic cap across every IC.

Way too high, not good for decoupling/bypass ... what I recommended is from the datasheet.

Where does the preference for low side switching come from?

NPN is ideal for low side switching (you linked to an NPN transistor), PNP is ideal for high side switching.

I think if you show your full circuit, you may get some good suggestions on how to enhance it, save pins, etc.

shazool:
Interesting ....

DTL is what was used in the olden days, before TTL. I remember seeing a few DTL circuits when I started work.

shazool:
Interesting, thank you for posting. I understand about half... what's the purpose of C1, R1, and R2? Why -12V instead of GND?

Without having done extensive circuit analysis, I'm guessing that R1 and -12V give more symmetrical switching times and/or less sensitivity to input signal level. C1 is a speed up capacitor that presents a lower impedance input to base on the input transition.

A similar topology should be workable with R1 & C1 deleted, R2 pulling down to Gnd, and an arbitrary positive operating voltage greater than a few volts.

For some applications, one could use diode logic, that is, just the "AND" with the diodes and pullup resistor on the left side of the circuit.

C1 decreases the turn on time as it acts like a short initially, hence lots of base current.

R2 discharges the base emitter capacitance at turn off time therefore decreases the turn off time.

-12v can be GND.

Is there some reason not to use a TTL or CMOS AND gate?

johnerrington:
Is there some reason not to use a TTL or CMOS AND gate?

Yes, it's quite possible that the OP doesn't need any gate at all, just doesn't know how to cascade shift register IC's.

True ----- it could have been done like this ---- (that's if we want to not see 0.7 V for 'low' output from diodes). Otherwise could just take the bottom side of the 12K resistor to be the AND 'output'.

dlloyd:
Wouldn’t need any extra MCU pins or AND gates/transistors with a wiring scheme similar to this. Just use one clock to shift all the data (3 bytes) in series and 3 latch pins (chip selects) to load what you want to appear on the parallel outputs.

Way too high, not good for decoupling/bypass … what I recommended is from the datasheet.

NPN is ideal for low side switching (you linked to an NPN transistor), PNP is ideal for high side switching.

I think if you show your full circuit, you may get some good suggestions on how to enhance it, save pins, etc.

My reasoning for not doing that must have been aiming for a ‘generic’ solution - faster, adding more registers won’t affect high-impedance period - when it really wasn’t necessary. Software engineering background isn’t doing me any favors here. I’ll do as you suggest and just cascade them all.

Oh, I had assumed that 0.01µF was just the minimum you should use. What happens when the capacitor is too large?

larryd:
C1 decreases the turn on time as it acts like a short initially, hence lots of base current.

R2 discharges the base emitter capacitance at turn off time therefore decreases the turn off time.

-12v can be GND.

Why not have it act like a short all the time (remove it and R1)? Wouldn’t that improve switching times even more?
And why not also use Schottky diodes with Vf lower than the transistor’s VBE(on) to immediately drain BE capacitance when an input goes LOW, turning it off instantly? Then R2 wouldn’t be needed either.

johnerrington:
Is there some reason not to use a TTL or CMOS AND gate?

No reason. I’d use one. I’m just trying to figure out why things are done the way they are.

Oh, I had assumed that 0.01µF was just the minimum you should use. What happens when the capacitor is too large?

Higher value capacitance will filter lower frequencies and won't work well for the fast transitions, ringing and noise on the signals for high speed CMOS ICs. Generally, I use 0.1µF ceramic capacitors, and yeah, this is mentioned in the datasheet for single supply ICs (section 11, page 16). Without them, strange things would start happening like data self-shifting, latch-ups, flickering or nothing.