Any ISE Design Suite Geniuses here?

I decided to do a project on a CPLD to get some experience with this. The purpose of the project is to build a 16-bit counter for up to four attached rotary encoders. I chose a Xilinx xc9572, downloaded ISE, got the USB-JTAG cable from Digilent, built a board with a 6 pin header, soldered on a socket, attached all the necessary power and JTAG connections to the XC9572, attached my hardware (4 rotary encoders, four switches - "reset", "center", "channel select 1" and "channel select 2", and 4 TIL311s for output). Digilent's programmer saw it fine first try and it is easy to program. I did a very simple design first that passed inputs directly to outputs and I could switch selections on the TIL311s. Worked, first try. Very impressive how easy this is to do.

So I worked up my main idea in schematic mode. The way it works is the same as a TTL circuit I made. It uses a positive clocked D flip-flop and a negative clocked JK flip-flop to decode the rotary encoder into two signals, a signal that gives direction and a signal that gives a count. This is fed to a 16 bit up/down presettable and resettable counter and the 16 lines off this counter are the output for the circuit. The "reset" button is tied to reset on the counter and the "center" button is tied to preset on the counter. And it works. Freaking amazing. It starts at 0000 and as I crank the encoder clockwise the output and TIL311s increase at the expected rate and decrease when turned counterclockwise.

So this is what is getting me. I want to duplicate the basic circuit with the two flip-flops and the counter three times and have another 48 outputs. But I don't want 64 outputs total, obviously, what I want to do is have the channel select determine which of the four sets of 16 outputs to send to the actual output pins (it already does this by sending the reset and preset signals to only the selected channel via a 2:4 decoder). My scheme for this is to put a 16-wide enable output buffer on each counter which is set to high-Z when not selected by the channel select (via a 2:4 decoder) and bus these signals all to the output bus. This would work on a real circuit but ISE hates it. It says I am creating a short even though the logic ensures that no more than one counter will be attached to the 16 bit output bus at a time because of the enable buffers.

Am I approaching this wrong? Any idea how to selectively select 16 out of 64 to a 16 bit output in ISE in schematic mode?

Here is a second question. For the "center" button I want to preset the selected channel (counter) to 8000H (32768) to put it in the center of the range. How can I provide a signal to the "in" bus on the counter (15:0) such that it is the bits 1000 0000 0000 0000? You would think this is easy and with other signals I just attach VCC or Gnd but for a bus, I just can't figure out how to do this in the schematic editor.

Thanks for any help.

Nevermind. Figured it out using busses and taps, splitting off the individual bits from the counter output busses and putting each through a 4:1 multiplexer. I wonder if this is efficient or not. So now I have the thing working with two channels and the report is:

Macrocells Used 54/72 (75%) Pterms Used 316/360 (88%) Registers Used 38/72 (53%) Pins Used 24/34 (71%) Function Block Inputs Used 104/216 (49%)

I think we are going to need a bigger CPLD to get this to 4 channels :frowning: