I don't see any decoupling caps(100nF) on the power pins for the various devices.
I didn't know about this practice, could you please tell me more about it? or suggest reading? and I just put it on the Vin pin of a device? or between VCC and GND?
Not sure where I'd find something. Best way I can describe is the 0.1uF provide local pockets of energy for each chip as they switch internally so they are not starved for power. Go from the power pin on each device (Vcc, Vdd +5, 3.3, whatever it is called) to Gnd.
I see a diode on the FTDI power interface - if someone plugs in a 5V USB/Serial adapter, that will put 4.3V on the VCC line, could be a problem with the rest of the board appearing to run at 3.3v based on the power header. Most 3.3V devices only want 3.6 to 3.8V Absolute max.
You are right, those 4.3V go to the Regulator Vin. Was that wrong?
That would be fine - can't tell from your schematic as it is not labelled. There are many unlabelled signals, having names on everything really helps in analyzing.
Rx & Tx need to be swapped on the FTDI header.
I'm a little confused here: I thought the FTDI's RX goes to arduino TX and vice versa. Is it wrong?
No, I was confused by names that look like RXI_TX and TXO_RX.
If the actual signal names are RX and TX, then you are fine.
CTS needs to connect to GND, that's an input to the FTDI chip, Clear To Send.
What is the Aref solder jumper for?
I was not sure if I must set my AnalogReference to external and connect it to VCC so I offered myself that possibility later.
Ok, so just pads then? Or connected to something? Signal names again.
Are there top & bottom layer ground planes? Hard to tell from the drawing.
Bottom plane is, but not the top. Do you advise to create a GND polygon on the top too?
Yes I do. Add some vias and Name them GND to connect the two layers.
Be sure to Name the layers GND as well.