I am currently searching for an Arduino clone with lots of IO. So far I understand that the Arduino Mega and Seeduino Mega would have enough IO. However they have 128k of Flash. This in turn implies that they have slightly different timing for some instructions (e.g. SBIC, SBIS). Since my current project relies on cycle accurate timing this is not really what I want. So I am searching for something like the megas with lots of IO but only 64k Ram. So far I found one board that would match my requirements. However it will cost almost 40 Euros.
For the "better" boards with the 128k processors I already found 20 USD boards.
It seems that their old boards featuring a 64 processor would have been what I am searching for. Does anyone know a source where I could get something like the old futurelec boards for a similar price?
This in turn implies that [AVRs with more than 64k of flash] have slightly different timing for some instructions (e.g. SBIC, SBIS).
Does it? I didn't see anything in the datasheet that says that. However, IO registers for your extra IO ports are likely to be beyond the range of ports that SBIS/SBIC can operate on, regardless of the amount of memory, reducing you to LDS/SBRC (2 cycles slower and uses a register.)
There is the RAMP banking registers for accessing RAM or Flash in devices with more than 64k, but that won't affect IO register access on the 1280 since there is far less than 64k of "data" space (The 128k of FLASH is in a separate address space.)
Neither of the 2 boards is an arduino clone (programmable from Arduino IDE and having an arduino bootloader).
The closest clones for your needs may be the sanguino http://sanguino.cc/
or duino644
@florinc With regard to the bootloader: this is true. But this is not really my concern. I could flash the bootloader anytime. However I do CLI arduino because I do not like the IDE. So most of the time I do not use the bootloader anymore. IMHO an ISCP is much more deterministic. So for me Arduino is a nice set of libraries around some AVR boards --> according to my definition almost any AVR board qualifies as an "Arduino" clone.
Right now I use something that would be a "Sanguino" clone. That is it features a 644p. However I am searching for something with more IO but without 128k flash.
@westf
With regard to the timing. According to the instruction set manual the SBIS / SBIC timing will be different. I guess this is not due to the register access. However I think it might have to do with the program counter which would need 17 bits. Then again the datasheet says the memory is organized in words, so 16 bits should be sufficient for the program counter. Then my conjecture would be false (and the datasheet unprecise).
So maybe the only way to really find out is to order a board with >128k and test it.
Still I would prefer a 64 or 644 board because migration is always somewhat anoying. Any hints for me?
implies that these board should be considered Arduino clones even with a more strict definition of Arduino like yours This can save quite some cash if you need several boards.
According to the instruction set manual the SBIS / SBIC timing will be different.
I'm still not seeing it. Can you point me to page and section/line numbers or something?
Both the 1280 and 168 datasheet say that SBIS executes in 1, 2 or 3 cycles, and the avr instruction reference says this is for for the don't skip case, skip single-word instruction, and skip double-word instruction cases. A double-word instruction would be something like LDS, containing a full 16bit address, not something dependent on memory size.
Words : 1 (2 bytes)
Cycles : 1 if condition is false (no skip)
2 if condition is true (skip is executed) and the instruction skipped is 1 word
3 if condition is true (skip is executed) and the instruction skipped is 2 words
Cycles XMEGA: 2 if condition is false (no skip)
3 if condition is true (skip is executed) and the instruction skipped is 1 word
4 if condition is true (skip is executed) and the instruction skipped is 2 words
I confess that I do not know the exact definition of XMEGA. But I thought XMEGA is equivalent to >64k flash. If not so, what is the definition of XMEGA? --> OK, I looked it up and obviously I was mistaken. So if I get this right an non XMEGA 128 would be OK for me as well.
Perfect.
Then I will order some of the futurelec 128 stamps
Thanks for this hint. Please correct me if I got it wrong.
Just one more question out of curiosity: why should the XMEGAs take one more cycle for this instruction? If it is not size of the adress register, what else would need this extra cycle?
By now you have figured out that the "XMEGA" AVRs are more than just the Mega AVRs with more than 64k of memory, and that therefore a "MEGA" Arduino or any of the similar large-AVR based development boards will give you the number of IOs you need without timing penalties.
why should the XMEGAs take one more cycle for this instruction?
One the the Xmega architecture's claims to fame is some sort of independent "io processor" that can operate completely independently of the CPU (even when the CPU is asleep, IIRC.) That implies that there is "stuff" in between the CPU and the IO ports, and it is not surprising that this stuff would slow down normal IO accesses to the ports.
(another possibility is that the extra cycle was needed just to allow the faster CPU clock rate. As CPUs get faster, it gets harder to talk to the outside world "at full speed."; a 3GHz Pentium-4 can't toggle an IO pin (even assuming it HAD IO pins) anywhere near 3GHz, and this is actually a common thorn in the side of many of the ARM cpus aimed at the embedded market. Embedded programmers tend to like nice deterministic timing, and the faster CPUs start to add uncertainty in flash access speed, uncertainty in caching of various sorts, uncertainty (or just slowness) in IO port access...)
Aha, sounds reasonable. Until today I was not aware that I can actually have an AVR running at 32 MHz. I have to keep this in mind the next time I run into performance issues. With twice the clock rate I can easily compensate for this cycle
Nice - but somewhat pointless for me. A bigger controller (as already discussed) will give me the required IO at a better price. And I do not need to stack shields which hopefully makes the whole contraption more reliable.
