I've been putting some thought into a cheap logic analyzer using easy to acquire chips (except for the sram) so that anyone with an arduino can put one together. Using HC components this circuit should easily handle 16mhz for arduino analyzing and with AC it could go up to 50mhz.
The basic schematics are here, in block form:
The probe circuits are split into two halves so the clock line can be fed into one half, then inverted and fed into the other to double the sampling rate.
A Mux enables clock selection either from source, arduino or an oscillator. For perfect arduino debugging you could pull the signal from
XTAL1 or 2. This is followed by a trigger circuit stage, which will probably be a simple rising edge trigger with a SR flip flop, but could easily be expanded with a mux to do other triggers (falling, change, bit sequence using an external clock + data line with a shift register + 8-bit comparator).
The XOR can act as a either a buffer or an inverter.
The counters act as an address counter for the SRam. The clock signal and the clock/2 are fed into the control logic. It's basically
- Advance counter + latch data 2. Write enabled 3. Nothing 4. Write disabled.
Easily implemented with a couple of logic chips
The SRam selection is important, I'm looking at the CY7C199 from cypress. It has a 10ns write time from valid address to finished write and is fairly cheap ~$2-4. 36k x 8bit means 64kbit samples for each probe line. For slower SRams you will be limited to a max clock of 500/write time MHz.
17-bits of counting are necessary 1 for the control logic, 15 for the address counter + 1 more to disable the clock once the address overflows.
Each probe input circuit is made up of only 4 chips and is stack-able, which is nice I think. It's limited by the fanout of the selected logic family at high frequencies though. However the circuit is exceedingly cheap, about $6 for parts, and that's per 4 probes.
74AHCT374 is my first choice for the flip-flops, the output enable is necessary to prevent interference when the arduino is reading data and it accepts ttl logic levels and 3.3v cmos. Plus it's nice and fast.
For all other components, if they are in the clock line they need to be able to withstand your max clock, for the arduino control chips (595s for mux selection etc, and 165s for reading the srams) they just need to be arduino compatible.
After both the clocks have been disabled the arduino can then shut off the clock, reset the counters, disable the latches, select output instead of input for the SRams and then increment the address counter, shift in the data and pipe it to the computer. Once it's finished it can reset the circuit, enable to clock etc.
I plan on prototyping this next week so, thoughts? suggestions?
