Hello,
Im trying to read 2 channels from the SAMD21,channels (A1,A2)and using INPUTSCAN.Looking at the arduino files it gives:
Heres the filepath for PC = C:\Users\yourname\AppData\Local\Arduino15\packages\arduino\hardware\samd\1.6.18\bootloaders\sofia\Bootloader_D21_Sofia_V2.1\src\ASF\sam0\utils\cmsis\samd21\include\component
And heres the section that pertains to INPUTSCAN:
#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFu << ADC_INPUTCTRL_INPUTSCAN_Pos)
#define ADC_INPUTCTRL_INPUTSCAN(value) ((ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)))
#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */
#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFu << ADC_INPUTCTRL_INPUTOFFSET_Pos)
#define ADC_INPUTCTRL_INPUTOFFSET(value) ((ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)))
Ive tried:
ADCsync();
ADC->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG_GND | ADC_INPUTCTRL_MUXPOS_PIN2;
ADCsync();
ADC->INPUTCTRL.bit.INPUTSCAN = 0x01; //config_adc.pin_scan.inputs_to_scan = 2; //(INPUTSCAN + 1) so Starts at PIN1 + offset(1),so PIN2. Then since Inputscan = Inputcan(1)+1=2,so PIN4.
ADCsync();
In my code,and it does read both channels but the samplerate is drastically reduced.Heres my entire ADC setup() code:
uint32_t fastADCsetup() {
//start at A1
ADCsync();
ADC->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG_GND | ADC_INPUTCTRL_MUXPOS_PIN2;
ADCsync();
ADC->INPUTCTRL.bit.INPUTSCAN = 0x01; //config_adc.pin_scan.inputs_to_scan = 2; //(INPUTSCAN + 1) so Starts at PIN1 + offset(1),so PIN2. Then since Inputscan = Inputcan(1)+1=2,so PIN4.
ADCsync();
ADCsync();
ADC->INPUTCTRL.bit.INPUTOFFSET = 0x00; //config_adc.pin_scan.offset_start_scan =0;
ADCsync();
//Set ADC reference source
ADCsync();
ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_INTVCC0_Val;// 2.2297 V Supply VDDANA //ADC_REFCTRL_REFSEL_INT1V_Val; // ref is 1 V band gap internal
// Set sample length and averaging
ADCsync();
ADC->AVGCTRL.reg = 0x00 ; //Single conversion no averaging
ADCsync();
ADC->SAMPCTRL.reg = 0x00; //Minimal sample length is 1/2 CLK_ADC cycle
// Set up clock to 8 Mhz oscillator
syncGCLK();
GCLK->CLKCTRL.reg = 0x431E; //enable GCLK for ADC, CLKGEN3 = 8 MHz oscillator
syncGCLK();
ADCsync();
ADC->CTRLB.reg = 0x400 ; // Prescale 64, 12 bit resolution, single conversion
// Enable ADC in control B register
ADCsync();
ADC->CTRLA.bit.ENABLE = 0x01;
}
Also,Im using CLKGEN(3) at 8Mhz,with a prescaler of 64.The code reads boths channels but doesnt increase my samplerate.Any pointers would be great.