Are DAC0 and DAC1 pins in hi-z state when they are not enable ?

Are DAC0 and DAC1 pins in hi-z state when they are not enable ? I am trying to find this info in SAM3X datasheet but I did not find anything about that. Does anybody know if I can expect DAC0 and DAC1 pins in high impedance when ADC feature are disable ? (with DACC_CHER=0x00000000)

PIO_MDSR register provides the multi-drive status of any pin (Sam3x datasheet, page 652)

ard_newbie:
PIO_MDSR register provides the multi-drive status of any pin (Sam3x datasheet, page 652)

Ooops… Sorry. I was looking only at DACC section… Thank you ard_newbie !