Atmega 328 crystal location.

I’m designing very slim pcb for use with the TLC5940 (20mm wide), so far I’ve been working on the plan for a single layer pcb but i came across a question.

Wheres is the best place to put the crystal and route the connections?
I have 2 versions with the crystal mounted on the end.
V1 runs the crystal lines around the outside of connections from the end to the XTAL pins.
V2 runs the Crystal lines underneath the mega to the XTAL pins.

Is there a problem with interference from the crystals lines being run around the outside?
(see the attached image for the v1 pcb.

Best crystal location is right next to the pins with short traces. See attached.

Can you mount the crstal and caps on the bottom of the board to make the traces shorter? Solder them in first, trim the leads, then install the uC.

AtmelAVR042 AVR Design Considerations.pdf (236 KB)

Unless you need accurate timing, a 3-terminal ceramic resonator will take up much less room than a crystal + caps

Are Resonators available as thru hole parts?

I guess so.

Or even less:

12 cents for both.

Little more space worth the tradeoff to me for accurate timing.
With a crystal, can write a time sketch that's good for a second a day drift.


I see from your picture that you are constrained for space and have a limited option on where to place the crystal. The rule is to position the crystal as close as possible to the prescribed pins.

The worst case scenario's are as follows:

Long track lines can become electromagnetic (EM) radiators which could fail your design if it were to go for Radiated Emission Tests at a certified test lab.

Another aspect to consider is electromagnetic (EM) susceptibility. Long tracks can act as receiving antennas i.e. imagine the design is implemented in a vechicle where Electromagnetic spikes from the spark plugs are a threat to your design. In this instance, a random spike could cause a glitch in the clock.

If possible, one could lay the circuit out on a 4 layer PCB such that the track lines are enclosed between two ground planes:
Layer 1 [top]
Layer 2 [gnd plane]
layer 3 [tracks from crystal to IC pins]
Layer 4 [gnd plane]

The gnd planes would act as an electromagnetic shield that would curtail electromagnetic emissions and as well as prevent the lines from being susceptable to electromagnetic interference

4 layer? Really?
Just put the crystal under the board, let its "flanges" overlap the items above without interfering.

Or, go surface mount with a few parts, put the uC in a socket and put the crystal, caps, reset pullup resistor/diode/DTR cap underneath it. Put the VCC/AVCC/AREF caps under the chip too.

Thanks DigitalRS and Cross roads.
I was still working in single layer format!
I think I will go duel layer and add it under the mega chip.

Thanks for the interference info, that was what I was looking for.

Even single layer, you can put the parts under the uC chip.