I have a question about the clock speed an ATmega chip can use...
I understand that I cannot run an Atmega at very low clock rates. My question is, why not? I think it is the opposite of overclocking. Is there any way to run an ATmega such as one Hz per second (I want to do this to further study its operation)?
Thanks!
A fully static processor design like the Z80 could be run at any lower-than-maximum clock speed you liked, and I've never tried it with an AVR, but since you have virtually no access to the useful internals, like the address or data bus or control signals (unlike a Z80), I've never seen the point
one Hz per second
s-1 s-1 ?
Maybe you mean 1Hz.
Yes, 1Hz, and double yes, Im working with the Z80 too. And since I can use the Z80 at any frequency, it is very easy for me to know how it works, but I think there are complications with AVRs. But I want to confirm if it is possible or if there is some trick to not break it.
If I'm reading the datasheet correctly for the 328p (for example), table 29-10, external clock drive, says that the minimum clock speed is 0Hz. Whether the internals function correctly whilst you are effectively single stepping the processor, I couldn't say.
There is a comment somewhere about not varying the clock speed between cycles...
There is not much interesting to see on a very slowly running avr...
westfw:
There is a comment somewhere about not varying the clock speed between cycles...There is not much interesting to see on a very slowly running avr...
Yeah - I have heard that AVRs don't like sudden step changes in operating frequency. I'm not sure how "sudden" is bad, though, and what that means at insanely low speeds. Micronucleus (the bootloader used on Digispark et al), on some parts, reaches the clock speed needed for USB by adjusting the internal oscillator far outside of normal range (eg, to 12.8 MHz, which is the lowest speed that it's supposed to work without a reliable clock (with a reliable, exact clock, it works at 12). But since the internal oscillator is also used for timing the internal write cycles, they have to turn it back down every time they get a page of data to write. The trick they use (and which apparently works) is to put a NOP (no operation) instruction immediately after writing the new speed to OSCCAL register; per datasheets, AVRs fetch an instruction one clock before it is executed. That, and the trick I described, leads me to belive that the already fetched instruction can get confused in some way.
That said, before I knew that trick, I was changing the clock speed around without that, and didn't have a problem (though I didn't run a huge number of tests).... I was changing the unique internal oscillator on the attiny841 (the relationship between OSCCAL1 and frequency is both very linear and very steep - and the 8 MHz factory cal is almost always well below the midpoint too; I haven't yet found a chip that wouldn't do 16, but I have one that has OSCCAL1 pinned at 255 to hit 16 at 3.3v) from 8 MHz to 16 and back 