Hello I'm using a Atmega1284p with the mighty core bootloader at 8Mhz, 3.3V.
Flashing the bootloader and uploading sketches via programmer works. The crystal has a clear 8Mhz Output and the Supply voltage is clean.
My issue is a:
avrdude: stk500_getsync() attempt 4 of 10: not in sync: resp=0xbe
When trying to upload via a FT232 on the board
Schematic
See attached schematic. Basically its just a FT232 wired up to the Mega. There is a switch to direct the FT232 to a ublox GPS module (to programm that by pc) but i tried with the right switch settings.
I've tried:
uploading a sketch via ISP -> works!
uploading a sketch via ISP that does a "Serial.println("hi")" loop. When connecting to Serial monitor (via the FT232) it works fine and i see the text
trying to unsolder the switch and solder directly -> Still no upload
trying to unsolder the switch and solder a Arduino Uno without the Dip inserted -> Still no Upload
trying various baud-rates -> Still no Upload
trying to unsolder reset line and add a button, tried to manual reset, -> Still no Upload
From my point of view the Serial part works perfectly, but there must be something different when uploading a sketch.
One quick silly thing - when you upload the sketch via ISP, that blows away any bootloader you had - you need to do burn bootloader after that to get UART uploads back.
DrAzzy:
One quick silly thing - when you upload the sketch via ISP, that blows away any bootloader you had - you need to do burn bootloader after that to get UART uploads back.
Oh.. really... would be a shame if that was the cause!
DrAzzy:
One quick silly thing - when you upload the sketch via ISP, that blows away any bootloader you had - you need to do burn bootloader after that to get UART uploads back.
You're a legend! Thank you. Problem solved. Now its working!
The circuit diagram posted, which appears to have been incomplete, showed the DTR outout of the FT232 directly connected to the reset pin of the ATMega1284.
My understaning is that DTR is pushed low at the start of the download process and remains low until the download is finished. Hence the reason for the 100nF capacitor between DTR and reset in the standard download circuit, when DTR initally goes low their is a short pulse only to reset the processor.
Does the use of an FT232 avoid the need for this capacitor ?
sgt_johnny:
The cap is there, but not in the image
You were asking for help with problems uploading to your 1284P, so its not helpful to post a so called schematic that is not of your board.
The _DTR output of the FT232RL is shown as directly connected to net RST which goes to the RESET pin on the 1284P, there is no cap in the circuit at all.