Little did I know that serial TTL was active low logic. Surprise on me.
RS232 serial is -V for 1 and +V for 0, TTL is as you have discovered reversed, HIGH for 1 LOW for 0.
Never did liked this.
(FYI, RS232 DCD, CTS, DSR are +V for 1 and -V for 0 :o )
Should be
(FYI, RS232 DCD, CTS, DSR are +V for asserted and -V for not asserted :o )
Master RX:
- Search on NAND OR gate, plenty of references.
- Pin 9 of each UNO slave to input of NAND OR gate, out of OR Gate to MEGA pin 19.
Master TX:
Mega Pin 18 to UNO slaves pin 8.
The above is difficult to visualize, it's best to supply a drawing.
Anyway, it’s good things are working now.