ATMEL Mega1284P evaluation board avalible

Ok, the board was autorouted with lots of parts placement manipulation to make traces as short a possible. Here's a blowup of the pads. I figured the top & bottom would be 2 solid planes connected by vias. Yet the tops got split up funny.

I make the ground traces thicker manually, they seem to revert to thinner every time I rip them up and let them play out again as I move parts around.

After the routing was done I tried adding polygon to make a ground plane.

What makes the ground plane actually connect to ground? The ground plane also made a couple of signals become disconnected. Not sure its doing much for me. Is there a better way to add that?

@pito, 1. There is no conflict - the battery holder is on the bottom of the board. All conflicts except for "stop mask" errors were taken care of, I will be cleaning up the Reference Designators next. 2. X1 on the DS1307? 3. 32K crystal has been layed over. Traces have been cleared away. 4. Am trying that again, see if it helps. 5. Went with a coin cell that I could easily find a holder for. 6. I don't know why Arduino original design had Aref located diaganolly opposite on the board from the Analog inputs. Ihave rerouted the Aref signal away from the power supply section. 7. Will review the 'big' electrolytics.

I'm trying to add the top & bottom layer hatch planes. I drew out the rectangles, renamed then Gnd, ripped up all traces and let the autorouter go - is ~97.7% done afeter Optimize 1. Having the 2 ground planes isn't helping the routing as much a I thought it would.

Great, so its all done finally, leaving me unrouted lines to clean up - all Grounds! Go figure.

Great, so its all done finally, leaving me unrouted lines to clean up - all Grounds! Go figure.

Shouldn't take too long.

Once you're done I'd have a manual tidy up of tracks (I'll have a play around with them if you want).

@Xroads: you have to simply write into eagle's command line: polygon Gnd (or GND or gnd - depends on the signal name) and it will assign the name to the polygon you intend to draw after..

BTW -you may place the crystal underneath the 1284p (see the dil40 machine pin socket there are such "windows"), I did it with dil28 narrow socket as well - Unless you plan to change the crystal too often it saves a lot of space. As the heights is concerned it fits nice..

BTW -you may place the crystal beneath the 1284p (see the dil40 machine pin socket there are such "windows"), I did it with dil28 narrow socket as well - Unless you plan to change the crystal too often it saves a lot of space. As the heights is concerned it fits nice..

Yeah I was going to suggest parts under the 1284 but I was struggling to think of anything that could go under it - I'd completely forgotten the crystal!

IC1 is also a good candidate to be put underneath the 1284p…
Btw, is the package of the IC1 really so wide??

pito: IC1 is also a good candidate to be put underneath the 1284p.. Btw, is the package of the IC1 really so wide??

You'd struggle to fit it under as it really is that wide - I think the plastic socket would hit it and that would make routing much harder without any real advantages.

Yes, the MAX232 driver chip selected is that wide. It would fit under the 1284 if the pins were laid perpindular to the DIP's pins, which would probabaly be good for the capacitors also. However I think routing of the signals in/out of the part then seriously get in the way of the 1284 signals on a 2 layer board. If I think about it tonight, I'll rip the traces up & try it. The decoupling caps and crystal caps and Reset R/C parts would then have to move out from under the 1284 (or go on the bottom of the board? Hadn't considered that possibility.) The MAX3232 also comes in a 16TSSOP package which the FTDI part type pin spacing. I went for the bigger hand-solderable size. The 16MHz crystal won't fit, is too tall.

@mowcius, "Shouldn't take too long. Once you're done I'd have a manual tidy up of tracks (I'll have a play around with them if you want)."

Its gonna be hard - there are so many signals, I did not see any readily available spaces to run a trace and vias to get them connected to ground somewhere, and I have hatching on the top & bottom layer. The pads that need to be connected are on their own little ground islands. I think I will have to move things a little and try again, should resolve 2 of the capacitor ground issues, getting ground to IC7 a little trickier now that the crystal caps are under the 1284.

I find it very hard to follow the traces after the hatching goes in.

I suppose I could have it do the routing with no hatching, strip out the grounds, clean up by hand, then let it try & put the hatching in again. Likely just leave me with unconnected grounds again.

Or just route it all by hand, just takes longer and results in more Design Rule checks to clean up as I tend to get things a little too close without realizing it (they look far enough apart when zoomed in!)

What gets me is the clearance errors that need cleaning up after the routing is done, and the Width & Dimension errors. from the libray parts! Specifically the fiduciarys, some interference between SD socket ground pad and hole in the lower right side, and vias that get placed too close to stuff.

I suppose I could have it do the routing with no hatching, strip out the grounds, clean up by hand, then let it try & put the hatching in again. Likely just leave me with unconnected grounds again.

Why are you hatching it then? Or just so it looks pretty...

Got it to work finally. Still had to make a few ground connections by hand, kinda like showing the program where to put a via or two so it could make the final connections. Moved a couple of caps slightly, moved a few traces so the ground planes could cover a little more area. Bit of an iterative process - tweak a trace or two, let the polygon refill. Move a part a scooch, let the polygon refill. Overall coverage between the 2 layers is good, got some voids in the bottom layer where the runs spanning long stretches don't give the polygon any access. Think I can add a via in the middle of the top layer and have it carry over to the bottom to get the voids filled?

Looking at parts for availability next - checking the SD socket to see if make can go in (digikey carries several, the mechanical drawings are not the easiest to interpret) or if the Sparkfun library part is unique.

When Eagle complains about "Clearance" errors around the regulator thermal pad, do I need to resolve that or can I ignore it as the top & bottom layers are intentionally connected together with vias?

I'm thinking this needs more work - looking closer, the top layer has a small pad in the middle that is isolated with an outer pad that is connectet to the ground hatching. The bottom pad is VCC, but is also connected to the bottom layer ground hatching. I need some way to isolate the regulator thermal pad.

if you shoot manually vias through you have to name each via according to the signal - in the thermal pad case "GND". You are missing the vias in thermal pad for the second voltage regulator.. The low profile crystal package fits under the chip.. Do use solid ground plane.. Generally : design rules - it depends on your pcb provider, most of them are checking them before the fab starts (and they shall provide you with their design rules definition, drill set definition etc..) and when they see an error they will not fab the pcb or they will charge additional fees.. :0 P.

Yeah, use a solid ground plane (or an almost solid ground plane if you absolutely have to stick silly hatching on it) and that routing's still ugly :D

What fab house are you thinking of using, go look if they provide design rules files - some do so you can easily check it yourself. ...and if the tracks are ground, you don't have to route them, rip them up and they will then just connect to the ground plane.

Ok, now that I've the hatched polygon figured out, I can try solid planes. I will check out naming the pads/vias as well. I had vias in both thermal pads, will check & see what happened to them. I might have just turned viewing them off when I did the screen captures.

There were a few pins that couldn't connect to the ground hatching because there were too many signal runs in the area. I had to run a trace by hand, adding vias to bring the signal under the part and back up to where there was a ground signal to hook up to. Just a little too complex for the autorouter.

I think part of the reason for the ugliness is the shield footprint. The placement of some signals is just poor, and the size of the 1284 means you can't cram everything all in the same spot.

Skyjumper just had some similar boards made (little bigger more connectors), the bare PCBs look good, I think I'll follow his lead as he's nearby (Boston area also) and they were made & returned pretty quick.

I think part of the reason for the ugliness is the shield footprint.

Nahh it's just the tracks going at funny angles.

Ah, the angles - thats all part of the shortest distance routing going on. The 40 pin DIP really stretches some of the signals out.

Hmm - I'd opt for a neat 45deg angle and a 1mm longer track any day but maybe that's just me

^^^ wot he sed ^^^

^^^ wot he sed ^^^

I’d also opt for a few ms longer typing time and correct spelling and grammar any day :smiley: