I'm having an issue with my sketch and I think the problem lies in the cut down example shown below to illustrate it;
I want to disable then re-enable an interrupt later in "loop", but it doesn't work. The Interrupts doesn't seem to be re-enabled.
What am I doing something wrong/illegal/stupid in the way this code is structured ?
Its on a 328 processor running 8Mhz external clock btw
Right. Just have a volatile, bool, flag to indicate whether the interrupt needs processing or not. If it's false, the ISR can just return immediately. If true, do whatever processing is required.
couple of things to consider there and have a play with - got stuck zoned in and needed some ways out
The code I listed is made up just to demonstrate and I mistakenly redeclared X1andX2 in loop - corrected that but now ( not that it matters to your suggestions so far )
just for the beauty of the language, I suggest you use true and false with your booleans instead of 1 and 0
also, as a boolean is a truth value, there is no need to compare to true (1 in your case) and the extra parenthesis are not needed when you write this:
if ( (X1) && (X2) == 1) ...
we usually would write
if (X1 && X2) ...
of course great variable names would help with self documenting code
Thanks all now sorted- The main thing was that is it was ok to do what I was doing with the Interrupts (starting in loop) and I was able to look elsewhere for the problems.
Some good tips I've used to tidy things up ( such as using local copied values of X1, X2) which makes it more bullett proof.
The actual issue was elsewhere in my code ( I had to use negative logic in one part and got that wrong, causing the code to hang inside a particular loop) and masking what I thought was a disabled interrupt.
Still looking for the original visio version; else, I have to re-make it.
VIL propagates through buffer-G1 and transmission path and probably picks up road noise and assumes VOL which must be below the forbidden zone to activate the next driven gate.
You have to cross the transition zone to get from one logic state to another, it's not so much forbidden as undefined. This is why most CPU logic is synchronous (clocked), and has setup and hold times.
In Fig-1 of post #13, the logic level is not switching from LOW-to-HIGH or HIGH-to-LOW. It is the same logic (here LOW) that is being propagated through a buffer gate (unity gain) and transmission path/wire. The figure intends to illustrate the meanings of VIL, VOL, VIH, and VOH.