I'm working on a project involving an ATTiny84, Ideally I'd like to have as many of its pins free as possible and don't want to have to try to squeeze a 16MHz crystal oscillator on to an otherwise small SMD based PCB design. But I know that ADCs often operate on a principle involving sampling and holding a voltage then seeing how long discharge takes. I know that without an external clocking crystal for the XTAL pins one can only do 8MHz, rather than the usual 16MHz, and that the accuracy of the timing becomes something like +/-10% on each "tick" of the internal clock rather than the parts per million accuracy one gets with a typical crystal. So, does the slower clocking and poorer timing accuracy affect ADC accuracy? Is the ADC dependent on the same clocking hardware as program timings and all the things usually considered time related, or does it not rely on the internal or external clock at all?, If it does rely on the overall chip's clock, and clocking uncertainty is 10% or even just 1%, that could really mess up the precision of some ADC measurements I'll need to make if this translates to 10% or 1% errors in the analogRead() readings.
Thanks
A few ADCs do, but most don't. The ATtiny84 ADC uses successive approximation and its accuracy does not depend on the clock speed, within reasonable limits. The data sheet has all the details.
How do you know this?
AVRs use successive approximation ADCs, essentially a DAC and a comparator.
Your description is of a dual slope converter.
The internet defines sample and hold as: "Sample and Hold is a circuit that is used to take a changing analog signal and literally hold it so that a following circuit or system such as an ADC, (Analog to Digital Converter) has the necessary time it needs to process it. At its simplest, a sample and hold circuit is a capacitor and a switch." This is the definition we used when designing them. The toughest part was finding an appropriate low leakage capacitor. We followed the sampling cap with generally a unity gain buffer but always a buffer. At this point the cap group was because of its internal leakage and the leakage of the opamp.
Also note when switching the mux (selecting a different channel) the charge is still on the internal cap and will either be charged by the new channel or discharge into that channel. For proper operation the A/D is specified at a maximum of 10K ohms. I would expect your error to be less then one count if going form 16 to 8 MHz.
You havent told us about the frequency characteristics of the signal you re trying to measure. If it changes quickly the slower clock speed could have an effect.
Thanks for clarifying, the signal only varies at a few hundrd Hz maximum and usually much less. I hadn't realised the ADC was timer independent, knowing that now I'm fairly sure it should work ok. Thanks.
You do need to considet the sampling rate - ie how often you measure the value.
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