ATTiny85 High Speed PWM

Other Hardware 3rd Party Boards
1

Hi all,

I'm working on a project to set up high speed pwm on the attiny85 using the PCK. My desired PWM frequency will eventually be 400kHz. However, after following the data sheet, timer/counter1 does not work. The interrupt flags are not setting and the counter is not resetting at the programmed value. If I remove the set up of PCK and use the system clock, the interrupt flags and PWM work correctly. I would really appreciate any help or thoughts

#include <avr/io.h>
#include <avr/interrupt.h>	

int main(void)
{
	PORTB = 0;		//Reset values on port B
	
	 //After setting up the timer counter, set the direction of the ports to output
	 DDRB |=  (1<<PB1) | (1<<PB0);	//Set the direction of PB1 to an output

	//PLLCSR - PLL control and status register: PLL is a clock multiplier - multiplies system 8Mhz by 8 to 64Mhz
	//         PLL is enabled when:PLLE bit is enabled, CKSEL fuse is programmed to 0001.  This clock is 
	//			switched off in sleep modes!
	PLLCSR |= (1<<PLLE);	//PLL enable
	
	//Wait until the PLOCK bit is enabled before allowing the PCK to be enabled
		while ((PLLCSR & (1<<PLOCK)) == 0x00)
	 {
		 //Do nothing until plock bit is set
	 }
	 
	 PLLCSR |= (1<<PCKE);		//Enable asynchronous mode, sets PWM clock source
	 
	//                    enable pwm              set source to pck              clear the pin when match with ocr1x
	TCCR1 =   (1<<CTC1) |
	                (1<<PWM1A)    |   
                       (1<<(CS10))       |        
                     (1<<COM1A1);
	GTCCR =   (1<<PWM1B) | (1<<COM1B1);
	
	 
	 //Set PWM TOP value - counter will count and reset after reaching this value
	 //			OCR1C
	 //400Khz	159		
	 //450khz	141
	 //500khz	127
	 OCR1C = 159;
	 
	 	 
	 //enable Timer1 OVF interrupt
	 TIMSK = (1<<OCIE1A) | (1<<TOIE1);	
	 
	 sei();
	 
	 //This should set the duty cycle to about 50%
	 OCR1A = 120;
	  
	
	unsigned int i = 0;
	 
    while(1)
    {
		
		//OCR1A = 0xFF/2;
		if ((TIFR | (1<<OCF1A)) == 1){
			i = i+1;
		}
		
	
    }
}
2

The PLOCK bit should be ignored during initial PLL lock-in sequence when PLL frequency overshoots and undershoots, before reaching steady state. The steady state is obtained within 100 ?s.

Try adding a 100us delay after setting PLLE.

3

I'll try adding that. I have the while loop there to wait until the PLOCK bit is set which is what is called for, but maybe it needs more time...

4

I setup a delay after the while loop, but to no effect. I think the while loop took care of waiting for the PLOCK to work. I think the issue has something to do with the clock set up. Does the system have to be at 8Mhz for the PCK to work? The CKDIV8 fuse is set from manufacturer, does this need to be removed?

Also, does the CKSEL fuse need to be changed? The data sheet mentions that for the PCK to work, the CKSEL needs to be either 0001 or 0010 (I think). However, I think that this is only for the system clock. Could this be the issue?

Thanks for the help

5

The solution to this issue is to program the device using HVSP and removing the default CKDIV8 fuse so that the system clock is actually 8Mhz. Alternatively, in the program the system clock prescaler can be set to 0 so that the controller operates at 8MHz.