Hope you can help with this...
I'm using an LT4356 in a design of mine, that drives an external NFET to actively clamp transients, like a TVS or varistor would. Datasheet here http://cds.linear.com/docs/en/datasheet/4356fa.pdf
However, you can also put N FETs back-to-back for reverse input protection too (Figure 7, Page 15), I've got the circuit drafted up in LTSpice, and it works - but, I don't understand what D1, Q3 and R7 are for - if I remove them from my simulation, the device still works with only a small deviation in output behavior?
Also, why is R5 such a large value resistance? Surely this means Q2 switches on much slower than Q1 as the gate capacitance can't be charged quickly through 1megOhm? ...but, typing that I may have just answered my own question - Q3 is there to help charge Q2's gate quickly?
So why not just remove D1, Q3, R7 & R5 altogether? (If I do this in Spice, I get a very unstable output voltage clamp)
The other thing, the datasheet says the gate pin is clamped to VOUT + 10V, but my SPICE simulation has the gate at 13V above VOUT?
EDIT - But the NPN transistor isn't getting a positive voltage on its' base, so how would it switch on? Furthur googling suggests this is a 'common base' type topology?