Back to Back NFET Question

Hi all,

Hope you can help with this...

I'm using an LT4356 in a design of mine, that drives an external NFET to actively clamp transients, like a TVS or varistor would. Datasheet here http://cds.linear.com/docs/en/datasheet/4356fa.pdf

However, you can also put N FETs back-to-back for reverse input protection too (Figure 7, Page 15), I've got the circuit drafted up in LTSpice, and it works - but, I don't understand what D1, Q3 and R7 are for - if I remove them from my simulation, the device still works with only a small deviation in output behavior?

Also, why is R5 such a large value resistance? Surely this means Q2 switches on much slower than Q1 as the gate capacitance can't be charged quickly through 1megOhm? ...but, typing that I may have just answered my own question - Q3 is there to help charge Q2's gate quickly?

So why not just remove D1, Q3, R7 & R5 altogether? (If I do this in Spice, I get a very unstable output voltage clamp)

The other thing, the datasheet says the gate pin is clamped to VOUT + 10V, but my SPICE simulation has the gate at 13V above VOUT?

EDIT - But the NPN transistor isn't getting a positive voltage on its' base, so how would it switch on? Furthur googling suggests this is a 'common base' type topology?

What actual circuit diagram are you talking about here. Page in the data sheet?

Figure 7, Page 15 - I had put that in my original post, but somehow deleted it. My apologies.

If I’m reading this correctly, Q3 is in a common base configuration and will turn on if the input (Vin) goes negative. It will then turn Q2 off. The reason R5 is so large is so that when Q2 gets turned off, the GATE output does not get drawn low.

D1 is to prevent the BE junction bias of Q3 from going negative under normal conditions as this would damage Q3. R7 is there to limit the current through Q3’s base.

So, you are right. Under normal conditions Q3, R7 and D1 will do nothing. However, if you remove them, the reverse input protection is lost.

Edit: Got my Qs mixed up.

I see, that makes sense! Thank you very much indeed.

However, regarding R5 - why would you wish to prevent pulling the gate low? Surely then Q1 would also just switch off? Which would be no bad thing, considering Q2 is being switched off?

Also, Q2 must turn on slowly with such a high resistance? - i’ll verify this tomorrow in SPICE.

jtw11: ...prevent pulling the gate low? Surely then Q1 would also just switch off? Which would be no bad thing, considering Q2 is being switched off?

Not pulling the gate of Q1 low, but the GATE output of the chip, which may not be a good thing.

Q3 does not have to turn on fast. It's body diode will ensure it conducts properly, and quickly under normal operating conditions. But it does need to turn off fast when Vin is negative.

Ah I see, so to prevent letting the gate output sink (or, actually source if connected to a lesser potential) excessive current by say allowing it a path to what becomes effectively a negative rail during a negative transient, thus damaging the gate pin?

I'm still at a loss regarding the gate voltage, Note 3 in the datasheet clearly says the gate is clamped to VOUT + 10v, yet my SPICE sims show VOUT + ~13V...

Thank you again, you've been a great help indeed!

EDIT - Typos... Tiny iPhone keyboard.

jtw11: Ah I see, so to prevent letting the gate output sink (or, actually source if connected to a lesser potential) excessive current by say allowing it a path to what becomes effectively a negative rail during a negative transient, thus damaging the gate pin?

Yes.

I'm still at a loss regarding the gate voltage, Note 3 in the datasheet clearly says the gate is clamped to VOUT + 10v, yet my SPICE sims show VOUT + ~13V...

Sorry, can't help you much with Spice. Perhaps one or more of the models is not 100%

Thank you again, you've been a great help indeed!

You're welcome.

Whilst redrawing my own schematics, I tend to use MOSFET symbols with the body diode included - makes things a little clearer.\

I'll get in touch with Linear, and see what they say about the gate voltage clamp.

On page 8 it says the Gate will be set to 14v above Out. Do not be concerned that you get 13v, be tolerant of variations in the voltages away from 13.0000000 volts or 14.0000000000 volts.

So it does - Note 3 infact says the gate is clamped to a MINIMUM of VOUT + 10V, not MAXIMUM. I must have read clamp, and immediately thought maximum.

Now I’ve arrived at another problem - not with the device itself, but rather with the application.

I’m supplying large amounts of current (in excess of 100A continuous, nominally 80A [fear not, distributed with large copper busbars, not PCB tracks]), and am supplying this with the output of the LT4356 circuit, using back to back multiple paralleled 0.001 RDSON FETs - however, i’m also supplying my control circuitrys power filtering and regulation with the same output - however, it’s just dawned on me, i’ll easily be getting large inductive transients on the output now fed into the more sensitive circuitry.

For example, low sided switching of some inductive load supplied by VOUT will now create a large transient on VOUT, destroying the next stage which regulates power for my MCU and other control circuitry.

I’m wondering if maybe I just need two of these devices, one for the high current supply and one for the control circuitry - I can isolate the control circuitry from a power down easily enough with a diode and bulk capacitance, but that dosen’t protect them from transients. I know I could just add a TVS on VOUT, but the whole point is dissipating the energy through the FETs - although I do need a TVS on the input anyway to protect against high voltage, low energy pulses above the abs max voltage of the device.

The other thing, applying a fast negative transient to the input, one still gets a small negative transient on the output according to the SPICE simulations, i’ll show some screenshots when I’m on my machine with SPICE - but a -100V transient still produces a roughly -40V transient on the output, albiet only for nS type time.