Behavior of LDOs in dropout

Long time lurker, first time poster.

I want to use a 3.7v LiPo battery to power an atmega328 + SD card. I'm thinking I will regulate the the power to 3.3V with an LT1763 so that the voltage doesn't exceed the SD card max of 3.6V. The dropout voltage of the LT1763 is around 200mV @ my max load of approx. 120mA, but I want to be able to use the battery until it discharges to around 3.3V.

When the battery voltage drops below 3.3V + 200mV dropout = 3.5V, will the LDO output clean power at the battery voltage - the dropout, or will it behave erratically? Are there other side effects , such as larger transient spikes during load switching or higher quiescent current draw?


In theory at dropout the p-FET or PNP transistor in the regulator will just be
fully driven trying to raise the output voltage, so it will follow the input voltage
less the small dropout.

Its not impossible for instability to occur though, since low dropout
regulators are usually non-linear and stability is a function of load and
somewhat of a compromise.

You may go with 3.0V regulator. Mind an SDcard can draw up to 200mA today..