Sup,
yes, I know this is probably not the place, but I can't think of better place at the moment:
How port manipulation works with official ST core?
I know that with Roger Clark core it's done like this:
GPIOB_BASE->BSRR = 0b1 << 9;
GPIOA_BASE->BSRR = 0b1 << 18;
How port manipulation works with official ST core?
It looks like it should be:
GPIOB->BSRR = 0b1 << 9;
GPIOA->BSRR = 0b1 << 18;
The xxx_BASE symbols are untyped in the ST CMSIS files.
Theoretically, that's the nice thing about "bare metal" - it stays the same despite philosophies about how to access it.
(Unless ST went and changed the GPIO ports in some of their chips. I checked the F1xx, L4xx, and F7xx includes, and they're all the same. But it could change...)
Thank you!
Compiler didn't gave me any errors, tho I'll test it with actual MCU tomorrow but I have no doubt it will work, thank you again.