I have attached a drawing of a divider circuit I'm trying to replicate. On the clock input, it shows what I thought was an AND gate (circled in red). It has the small circle along with another line, so I thought it was perhaps a NAND gate, but I have not seen this symbol layout elsewhere (one line to the left and two lines to the right of the symbol). The text of the design mentions "The first technique requires a differential clock, that has a 50% duty cycle, a extra Flip Flop, and a gate to allow Odd integers, such as 3, 5, 7, 9, to have 50% duty cycle outputs and a synchronous clock."
Obviously the clock line is an input, so there are two output options which are sent to the clock inputs on the flip-flops shown. I have not found either an AND gate or NAND gate with one input and two outputs. Are they bi-directional, i.e. a two input/one output could be reversed?
I have not found either an AND gate or NAND gate with one input and two outputs. Are they bi-directional, i.e. a two input/one output could be reversed?
My take on that circuit is that the clock 'gate' (the one you circled) is showing the logic required, not nessesarily that a specific chip is avalible to perform that function. I'm sure that there is somewhere some obscure chip that takes a single input and outputs both the same signal and an inverted copy of the signal, probably called a 'clock driver' chip.
I think the logic would be satisfied if the clock input signal was directly wired to the reset pins of the first two flip-flops and the same clock input signal was also wired to an inverter then on to the third flip-flop, that the whole circuit would function as designed.
I'm laying out the circuit w/ an inverter. As a follow-up question, do I utilize the CLK inputs on the first two flip-flops, i.e. tee the CLK line to them and the R pins or just connect the CLK pins to Vss along with other unused inputs?
2Wheeler:
I'm laying out the circuit w/ an inverter. As a follow-up question, do I utilize the CLK inputs on the first two flip-flops, i.e. tee the CLK line to them and the R pins or just connect the CLK pins to Vss along with other unused inputs?
I was in error when I said the clock signal goes to the reset pins of the FFs. The external clock signal should wire directly to the both clock input pins of the first two FFs, and an inverted copy of the same clock signal should wire to the clock input pin of the third FF. The R and S (direct reset and direct clear) pins can just be left unconnected (or wired to Vcc) assuming you are using some flavor of a TTL 7474 type D flip-flop.
Why not save a chip - use a 2 input QUAD NAND with 1 gate in series on the output as inverter to make it function as AND, and use third gate as your inverter.
You show your supply voltage going THRU the filter caps - you instead need the caps in parallel, with one side connected to in (and out) and the other side to ground.
I don't believe a 12V regulator with a 12V input will give you much regulation - perhaps consider a 5/6/9 volt output instead?
CrossRoads:
why not...use a 2 input QUAD NAND with 1 gate in series on the output as inverter to make it function as AND, and use third gate as your inverter
And, while you are at it: Instead of getting the output from an OR gate connected to the Q outputs of the last two flip-flops, you can use the fourth NAND gate to generate the same signal by connecting it to the Q-bar outputs. Reference: De Morgan's laws
ClkOut = q2 .OR. q3
Same as
ClkOut = .NOT. ( (.NOT. q2) .AND. (.NOT. q3) )
Total parts count for the divide-by-three counter circuit:
One '4011 Quad Two-Input Nand Gate (or equivalent).
Two '4013 Dual D-type Flip-Flop (or equivalent).
(If you don't need operating voltages above 5 Volts, you might consider 74xx family devices: 74xx00 Quad Two-Input NAND gate and 74xx74 Dual D-type Flip-Flop.)
Final note:
Unused inputs, for CMOS devices should never be left open. The '4013 devices have active-high reset pins and active-high set pins, so they should be tied low in this application. The 74xx74 devices have active-low set and reset pins, so they should be tied high in this application. Other unused inputs can be tied high or low, but none should be left floating.
Regards,
Dave
Footnotes:
"It's all just Smoke and Mirrors"
---Black Veil Brides
"It's all just NAND gates and D-type Flip-Flops."
---davekw7x
You still need a cap on the output of the regulator to prevent output oscillations. Several other recent threads had just that problem. See the 7805 data sheet.
Ideally you would also have a decoupling cap, 0.1uF (100nF), across VCC/GND of each chip as local power storage buffer.
Depending on how RF noisy the final environent is, you may not notice anything without them. Or, the counting may appear to be upset.
I am using Cadsoft Eagle Version 5.1, which has an option to print to a PDF file.
Earlier versions did not have that, and I used Acrobat Distiller as print target to create documentation for distribution. (The pdf files from Eagle are smaller than what I used to get from Acrobat.)
to tee it into both CLK inputs to maintain what was happening in the example circuit.