Just to add to what aarg said, the interrupt could be missed if too long a time elapses. For example, if you turn off interrupts (for whatever reason) for a second, then multiple timer interrupts would be missed, as the first event sets the "there is a timer interrupt flag", and when the second event occurs, the flag is already set, so it can't be set again.
Basically the processor would have a state machine internally, and at the completion of each instruction (which may be one or more clock cycles) it would check, if interrupts are enabled, all of the interrupt flags for things like timers, serial comms, SPI, etc. When it finds one set, it then enters interrupt processing for that interrupt. The order in which it does these tests (which is documented in the datasheet) is effectively the interrupt priority.
If multiple interrupt flags are set, then the lower priority ones will still be done - eventually - but not necessarily the moment that the event that triggers the flag being set happens.