Can Someone Knowledgeable “Explain” the ESP8266?

As topic title suggests, I’m a little confused by this family of devices. I have used it successfully in several projects that include web servers, Blynk user interfaces, and I2C / SPI peripherals. So, I don’t have a problem using it, there’s just a couple things I don’t get:

First, where’s the REAL datasheet? If I go to the Atmel or Freescale web site and download a processor’s datasheet, it’s hundreds (or thousands) of pages long. There will be detailed descriptions of register maps explaining the function of each bit field. There will be chapters describing all the internal resources such as timers / counters, SPI interfaces, internal buses, interrupt controllers, etc. Most of the “datasheets” I see online for ESP8266-based devices are 20 or 30 pages long. Where’s the rest of it? Is everything available in one place, or is the information spread around?

Second, and more specifically, how does instruction fetching work with this processor? It doesn’t have internal Flash, but connects to an external SPI Flash. So, how does instruction fetching from SPI keep up with an 80 MHz processor? Are chunks of Flash pre-fetched into internal RAM?

Thanks for your help.

Perhaps the ESP8266 Forum will have your answers

I think the most detailed document I have is one which is titled "ESP8266EX Hardware User Guide" but it is only 48 pages long.

Kolban's ESP8266 book has a lot of useful stuff


here are all the official docs. use More+ button on the bottom.[]=14

For question 2, the esp also has internal rom, and ram. Some of the ram implements cache memory that sits in front of the spi flash.

For q1, well, welcome to China. Pleas send your (Chinese-speaking) engineers to speak with the expressif engineers if you need more detailed technical info. (Come to think of it, Intel is not so different.)

and perhaps Tensilica L106 datasheet is applicable

Could you find an l106 datasheet? There is apparently an announcement of the micro106 architecture, which does not have cache so perhaps isn’t exactly correct. People who have looked further have apparently not found anything, and the architecture is extensible beyond the core definition... otoh, it’s apparently able to use the stock xtensa gcc, so it can’t be too far off.