Cannot Upload with Reset Lines Linked!

Hi,

Here's some feedback on a nasty programming design issue with the Freetronics EtherMega board. It likely also affects other boards with the same reset circuit design.

I have a project using two EtherMega boards plugged into a custom PCB. The custom PCB has CPLD's, 16 Bit ADC's (7) and 16 bit DAC's (2) to monitor power and control loads.

One of the CPLD's generates an 8kHz pulse train to: 1. Trigger the ADC's to do a simultaneous conversion 2. 12us later it triggers Int0 on the Mega board.

Inside the Int0 service routine I read all the ADC's and write to the DAC's + do some maths on some of the values. To read the ADC's I'm doing read/modify/write actions on the Port E pins. The ISR takes 17us to execute.

The problem was I could not upload a sketch to the board. The RX LED gives one flash then stops and the IDE eventually times out with a stk500v2_getsync():timeout

I thought it might be to do with Int0 active and the read/modify/write to Port E. If I unplug the board so there is no Int0 activity and therefore no read/modify/write to Port E the the board programs fine.

I thought the interrupt driven read/modify/write to Port E must be killing the serial comms from the programming tool in the IDE.

I am also using serial 1 to talk to another device and have no problem with read/modify/write to pins on Port D - it's not mucking up the serial comms. So I wonder if this is the problem...

I have nothing connected to pins 0 & 1 (Serial RX/TX).

So, I went looking. First thing was to check the reset pulse generated by the Atmega8u2 chip for programming. It was generating it ok but it was only pulling down to 50% on the main reset line.

I have the reset lines linked on both EhterMega boards and also run off to an open drain reset generator chip on my main board + the CPLD's to generate a know startup state.

It appears the Atmega8u2 programming chip reset line pulls low and stays low during programming. It uses a 100nF cap to create a short low pulse on the reset line. If both boards have their reset line connected together then the 100nF cap on the other board forms a capacitor divider network limiting the reset pulse to 50% rail - so no reset level is reached and the board does not reset.

The reset system for programming works fine if only one board is ever used and the reset line not used externally. It's a bit of a design screw-up if more than one board is to be used or additional loads are added to the reset line.

It would be better to use an open collector or open drain to momentarily pull the reset low. To get things going I just cut the track to one of the EtherMega board reset pins on my main board.