Cascading 100 74hc595 with displays

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1

Hello, I have a problem with cascading 50 modules like this: Display Module 7-Segment 2 Digit with 74HC595

Project describtion:
ESM8266 Node MCU V3 is connected to 50 modules linked above, the wifi module is connected only to the first display module and the first display module is cascaded to second display module. To power it i use PC PSU, im almost sure the power isnt a problem, because now it works with 10 wifi modules (5 display module for each wifi).

Problem:
When I connect 5 display modules everything works fine, but when i add more displays (it starts to mess up with 10 displays) it stops working. The first thing is that the bits starts to shift or something and additional segments on displays appear (Most often dots, the first/last bit). When i connect even more displays everything starts to shift and its just a big mess with random segments turned on, whats more funny not only added modules are broken, but all of them. For example adding 11 display module break all the modules. Another thing, i see some patterns in how it breaks, for example on module 2 there is sometimes additional dot when sending digit "1", and there isnt while sending "2" and it shifts to another module.

Solutions that i tried:

  • Wire connection isnt a problem, i checked like 10000 times
  • There is enough power, it can run 50 displays with 10 Wi-fis easily
  • Display or wifi modules aren't destoryed, tested in set of 5 everything works
  • I tried to slow down the code, it didnt work
  • The data in the code (bits) are correct

What is my futher guess:
I think it might be connected with signal losing it "strenght", i'm not familiar with theory and i dont know how to operate with digital signals.

Parts of code:

#include <Arduino.h>
#include <ESP8266WiFi.h>
#include <ESP8266WiFiMulti.h>
#include <ESP8266HTTPClient.h>
#include <WiFiClient.h>
ESP8266WiFiMulti wifiMulti;

const int latchPin = 2;
const int clockPin = 12;
const int dataPin = 14;
uint8_t  numberB[] = {B11000000, //0                  _8_
                      B11111001, //1                3|   |7
                      B10100100, //2                 |_2_|
                      B10110000, //3                4|   |6
                      B10011001, //4                 |_5_|.1
                      B10010010, //5
                      B10000010, //6
                      B11111000, //7
                      B10000000, //8
                      B10011000, //9
                      B11111111, //10 blank
                      B10000110, //11 E
                      B00101111  //12 r.
                     };

void updateDisps() {
  digitalWrite(latchPin, LOW);
  for(int i = endIndex; i >= startIndex; i--){
      dispNum(dataArr[i]);
      delay(10);
    }
  digitalWrite(latchPin, HIGH);
}

void dispNum(int numInt) {
  //   _ _ = (digit2) (digit1)]
  int clockDelay = 10000;
  if (numInt == -1) {   // -1  =>  Er.
    shiftOut(dataPin, clockPin, MSBFIRST, numberB[12]);
    delay(10);
    shiftOut(dataPin, clockPin, MSBFIRST, numberB[11]);
    return;
  }
  
  int digit2 = numInt / 10;
  int digit1 = numInt % 10;
  if (digit2 != 0) {  // [2 3] v [2 0]
    shiftOut(dataPin, clockPin, MSBFIRST, numberB[digit1]);
    delay(10);
    shiftOut(dataPin, clockPin, MSBFIRST, numberB[digit2]);
  }
  else { // [_ 1] v [_ _]
    if (digit1 != 0 ) { // [_ 1]
      shiftOut(dataPin, clockPin, MSBFIRST, numberB[digit1]);
      delay(10);
      shiftOut(dataPin, clockPin, MSBFIRST, numberB[10]);
    }
    else { // [_ _]
      shiftOut(dataPin, clockPin, MSBFIRST, numberB[10]);
      delay(10);
      shiftOut(dataPin, clockPin, MSBFIRST, numberB[10]);
    }
  }
}

I can't fix it and i'm trying for a while and I really need help with this :((.

2

yes, you need driver(buffer, amplifier) for Latch and clock lines, for each block of 5 modules.

3

Thanks!
Could You link me your suggestion what should i use? And why only for Latch/Clock lines? Can you share me some materials or keywords what should i search?

4

keywords "transistor"

5

@kolaha's transistor, or simply one or two logic ports with good drive capability. Something like a Schmitt trigger, AND etc.

6

Because presumably you have the latch pins from all the 74HC595 connected to one port pin. Same for clock pins. One port pin can't drive so many inputs.

7

Have you installed decoupling caps?

8

Yes, every display module has 2 caps (i think so).

9

What about data line? Every display module has 5 inputs and 5 outputs, VCC, GND, Latch, Clock and Data in/out.

10

Oh I'm sorry. I incorrectly assumed you wanted different numbers on each module and could daisy chain the 74HC595s. Now I see those modules don't have an output bit to allow daisy chaining. After checking the code I assume you want all the modules to display the same number

11

There are pads, some arrangement for a header etc on two sides. There's no DWG SCH, but I suspect the hidden (obscured) side has "DO" for the succeeding stage/s.

12

You were right, i want to display different digits and it works because each display module has shiftout as data_out that is connected to data_in to another display_module.

So read about schmitt trigger, do you still consider it as a worth to try solution?

What do you think about that the shift registers desync being a reason why the data is incorrect, and how to sync it if its a problem?

13

Also i wonder if this CD74ACT14E shmitt inverter is a good solution and if i should give it a try

14

Perhaps explain how you figure that it might.

15

I read more about it as @rsmls suggested and if i understand it correctly it eliminates noise and makes the signal stronger. I dont know what do u expect me to tell. So is is a valid solution, cuz You didnt answered.

16

Yes, depending on the type used.

It doesn't look like it can source all that much more current than a microcontroller GPIO. So I don't expect this to work all that better than a bare Arduino.

In your place, I'd probably give it a go with a regular transistor (or two, to make the thing non-inverting). See if that works. If not, you can always get a dedicated line driver, but I suspect an arrangement like this would work OK:
image
You can use generic NPN small signal like 2n3904, 2n2222 etc. Alternatively, you could use MOSFETs instead, but the arrangement would be slightly different.
The value of R3 of 68R is on the low side for 5V logic and likely even excessive for 3.3V logic, but it should have no trouble driving your arrangement of data pins.

17

That's why I don't think you need to buffer your data out IO pin, because it's only driving one thing.

It wasn't me that suggested that solution. I'll let others discuss it with you.

Same as my comment above, I don't know what would be a good solution ATM. It could be to do with insufficient buffering of clock / load signals, something to do with propagation delays down the chain of shift out on one module connected to shift in of the next module, or something else I haven't thought of.

18

What I'm concerned about is that the presence of data_in/data_out and clk_in/clk_out on those modules does not mean the outputs are buffered. If the data_out pin is an overflow from the previous module, then yes, that one should be fine. However, it's entirely possible (likely) that the clock lines are all connected in parallel.

It would be nice to put a scope on both of those lines (but CLK in particular) and see to what extent the signal degrades as modules are added.

19

I'm thinking:

  1. One GPIO pin is driving all the clocks. The drive capability of that pin may not be sufficient to drive all the modules' clock inputs.
  2. Similarly for the GPIO pin driving all the load pins.
  3. From a loading point of view, the data GPIO pin shouldn't be a problem because it's only driving one module's input.
  4. The normal method of daisy chaining 74HC595s is implemented by the modules. I.E. The 74HC595 QH output of one module goes to the 74HC595 SER input of the next module.
  5. I've not checked whether the propagation delays could be a problem.

Are talking about the same thing? Or am I misunderstanding what you said?

1 Like
20

Another gate will still have fan-out limitations.
Maybe a gate driver (like a MIC4427 or sim) - if that's what's going on.