Cascading Delay

Hi all,

I am really new so please don’t mind if this is a dumb question.

I have cascaded 15 shift register and was testing them with a dummy code (given below). All is working fine the only problem being that all the ICs arehave syncronised outputs except when it goes from 12th to the 13th IC. When it overflows to the 13th IC it is delayed bye one clock cycle. After this the outputs are all fine and syncronised. Attached is a image from a logic analyzer. I would be really glad if some one can help me know the reason for this delay.

Please note that the code i was using is not meant for this application. It was just for testing purpose.

int dataPin = 2;        //Define which pins will be used for the Shift Register control
int latchPin = 3;
int clockPin = 4;

int seq1[14] = {1,2,4,8,16,32,64,128,64,32,16,8,4,2};         //The array for storing the byte #1 value
int seq2[14] = {128,64,32,16,8,4,2,1,2,4,8,16,32,64};         //The array for storing the byte #2 value

void setup()
{
    pinMode(dataPin, OUTPUT);       //Configure each IO Pin
    pinMode(latchPin, OUTPUT);
    pinMode(clockPin, OUTPUT);
}

void loop()
{
    for (int x = 0; x < 14; x++)         //Array Index
    {
        digitalWrite(latchPin, LOW);                               //Pull latch LOW to start sending data
        shiftOut(dataPin, clockPin, MSBFIRST, seq1[x]);            //Send the data byte 1
        shiftOut(dataPin, clockPin, MSBFIRST, seq2[x]);            //Send the data byte 2
        digitalWrite(latchPin, HIGH);                              //Pull latch HIGH to stop sending data
        delay(75);
    }
}

Thanks in advance guys

rhl

I do not see any attached picture. Also: what do you mean by "delayed by one clock cycle"? As I see it you have a "delay(75)" which will delay significantly longer than just one clock cycle.

Why not put a small delay here instead

        shiftOut(dataPin, clockPin, MSBFIRST, seq2[x]);            //Send the data byte 2
>> small delay
        digitalWrite(latchPin, HIGH);                              //Pull latch HIGH to stop sending data
        delay(75);

to give the data chance to ripple thru before latching it?

Hey Klein and CrossRoads.. thanks for replying..

Here is a pic for the same hope this helps. Delay is not in the code timing but with the transfer of data from the 12th to the 13th shift register. With the rest of the shiftregiser ( from 1st -12th & 13th - 15th) its working fine.

hope this helps...

Now you still need to tell us your circuit schematic and where the A1-A8 pins of your logic analyzer are connected.

rhl.thakur:
Delay is not in the code timing but with the transfer of data from the 12th to the 13th shift register.

Crossroads is saying that there’s a non-zero time that the shift register takes between shifting in the data and shifting it out again; datasheets for shift registers are riddled with timing values for this. In your case that time is adding up and by the time it gets to the 12th register it falls behind a clock.

Follow Crossroads’ suggestion. If that doesn’t work you might need to write a custom shiftOut function that clocks the data out more slowly:

void myShiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, byte val)
{
	int i;

	for (i = 0; i < 8; i++)  {
		if (bitOrder == LSBFIRST)
			digitalWrite(dataPin, !!(val & (1 << i)));
		else
			digitalWrite(dataPin, !!(val & (1 << (7 - i))));

                      delayMicroseconds(50);  // slow it down here
   
		digitalWrite(clockPin, HIGH);   
		digitalWrite(clockPin, LOW);
	}
}

Hey Thanks a ton CrossRoads now i get it better waht you were trying to explain.

Will try this and get back with the results.

Thanks