CCD control and clock generation


My current project is to build a control board for this specific CCD sensor : I already have a functionnal board from a manufacturer but I am not satisfied. So, I figured that it would be fun to redesign the board to fit my requirements.

I decided to use An arduino Due as the main controller. Its tasks would be : - Interfacing with a Host PC - Receive the output of an external 16 bit ADC - Perform some noise reduction and Correlated double sampling - Manage the data transfer bus ( buffer 20 kBytes packets or more and send them trough the native usb port)

Now I also need to generate a total of 9 clocks at multiple voltages in order to drive the CCD sensor. Three of them are running at 28.64 MHz, the others are slower ( in the range of 10 kHz) . This is probably out of reach of the Arduino Due, so I don't really know how I could perform this task. I see two possibilities : - An FPGA could be a solution but it could also perform the Due's work so it seems a bit useless to combine it with a Due... Plus, I know nearly nothing about them. - A specific IC with oscillator and included PLL.

My choice would be the FPGA because it is extremely flexible, it can synchronize the clocks, distribute them and I like to learn. And mixing it with a Due could help keep things "simple" for a first protoype. But again, I really am no expert here, so your input could be helpfull, especially in the choice of a specific component.

Sounds like a technically challenging project, most of which isnt really related to the micro controller

For the FPGA you could look at this.

Its actually an ATMega32U4 (as use on the Leonardo and Micro Arduino's with a XILIX Spartan attached, and an SD card to store the "program" for the FPGA.

The ATMega32U4 is programmed to appear as external storage to the host computer i.e the PC. to make uploading of the FPGA code easier, but you may be able to reprogram the 32U4 to do the tasks that you were going to do with the Due.

I've no knowledge of click generators, but finding a single device that can generated 9 different clock frequencies (I presume with specific delays etc), is probably going to be a tough job. So I suspect that the FPGA route is the best one.