10.2 Design and Programming of TCNT2 Module based high frequency (say: 62.5 kHz) PWM signal
High frequency PWM signals are well suited for power regulation, rectification etc. When using high frequency chopping for the inverters, the component size for the filter design are relatively smaller and thus there is a good reduction in system cost.
(1) Fig-10.3 presents the PWM hardware for the TCNT2 at conceptual level. We will frequently refer to this diagram during the design phase of the PWM signal in Step-3.
Figure-10.3: PWM hardware of TCNT2 at conceptual level
(2) Fig-10.4 depicts various wave-forms related with the synthesis of high frequency PWM signal using channel-A of TCNT2. We will frequently refer to this diagram during the design phase of the PWM signal in Step-3.
Figure-10.4: PWM related wave-forms for TCNT2 for Mode-3 operation
(3) Let us gather design related data through questions and answers:
a. How many wave forms are there in Fig-10.4? Which one is the PWM signal? Ans: 5, waveform-4/5.
b. What is the symbolic name of the period of the PWM signal of Fig-10.4? Ans: T.
c. At which DPin of Fig-10.3, the PWM signal of Fig-10.4 will appear? Ans: 11.
d. Which switch of Fig-10.3 should remain closed for the PWM signal to move towards external DPin-11? Ans: S3.
e. Which gate in Fig-10.3 should be at closed condition so that the PWM signal will really appear on DPin-11? Ans:
f. How many clkTC2 pulses would be counted by TCNT2 of Fig-10.3 upto the point of over-flow? Ans: 256.
g. Assume clkTC2 is 16 MHz (fOSC/N). How much is T in Fig-10.4? Ans: 16 us.
h. What is the frequency of the PWM signal of Fig-10.4? Ans: 62500 Hz.
i. Given: fosc = 16 MHz; N = TC2 Prescaler division factor. Find equation for the frequency (fOC2A) of PWM signal of Fig-10.4 in terms of fosc and N.
fOC2A = 1/T = 1/(time to count 256 clkTC2 pulses) //clkcTC2 = 16 MHz/1 = 16 MHz
==> fOC2A = 1/timeDelay.
==> timeDelay = (1/16000000)256
==> timeDelay = (1/(clkTC2)256) = 256/(fOSC/N) = (N256)/fOSC
==> fOC2A = 1/timeDelay = fOSC/N256
j. We wish to set the ON-period of the PWM signal at 4 us. How many clkTC2 pulses should be counted by TCNT2 before the logic level of PWM signal at DPin-11 drops to LOW level? At what point of the line "P-Q-Q1-R-S", will the PWM signal be dropping to logic LOW? (Assume: TC2 Prescaler division factor, N = 1). Ans: 64, Q.
k. Assume that the event of Step-10 has happened, and now the logic level of PWM signal at DPin-11 must go back to HIGH level again to complete the cycle/period of the PWM signal. AT what point of Fig-10.4 (along the line of P-Q-Q1-R-S) should it happen? Ans: point-R.
l. What is the resolution of the PWM signal of Fig-10.4? (Resolution refers to the minimum amount of time by which the ON_period of the PWM signal could be increased.) Ans: 0.0625 us. This is the time required to count 1-pulse of clkTC2 which is 16 MHz.
m. Which "logic gate" of Fig-10.3 should remain closed for the PWM signal to appear on DPin-11? Ans: G2.
n. To change ON-time of the PWM signal of Fig-10.4, write down the name of the point (P, Q, Q1, R, S, ?) which will change its position along "P-Q-Q1-R-S" line. Ans: point-Q
o. How is the Q-point along the counting up line "P-Q-Q1-R-S" of TCNT2 determined?
Ans: TCNT2 begins counting along the line "P-Q-Q1-R-S" and when its content matches (becomes equal) with the content of OCR2A Register, the PWM signal drops to LOW level. If we have intially kept 32 (0x20) into the OCR2A register, the Q-point will appear after 2 us. This means that the ON-time of the PWM is 2 us. After that the TCNT2 keeps counting up and when it reaches at "total count", the PWM signal comes bbcak to HIGH level.
p. Write the symbolic name and the full name of the register with which the current content of TCNT2 Register should be compared so that when a match occurs (the contents of these two registers: TCNT2 and ? are equal), the logic level of DPin-11 will drop form HIGH to LOW. Ans: OCR2A, "Output Compare Register of TC2 for Channel-A".
q. Look at Fig-10.3 and tell the name of the register whose content regulates the duty cycle of the PWM signal of Fig-10.4 Ans: OCR2A.
r. The PWM signal of Fig-10.4 is known as SSFPWM signal -- "Single Slope (SS)" "Fast (Fast changing = high frequency = 62.50 kHz)", "PWM" signal. Present the names of the registers which when initialized/configured correctly, the PWM signal of Fig-10.4 appears on DPin-11 of Fig-10.3.
Ans: TCCR2A, TCCR2B, and OCR2A.
s. Look at waveform-3 of Fig-10.4 and then tell/write the name of the flag that will assume HIGH when PWM signal goes to LOW at point-Q along the P-R-S line of waveform-1. Ans: OCF2A (Output Compare Flag for Channel-A of TC2).
t. Look at waveform-2 of Fig-10.4 and then tell/write the name of the flag that will assume HIGH when TC2 finishes "total count". At what point the over-flow event does happen along the P-R-S line which results in bringing back the PWM line at HIGH level and thus completes the cycle? Ans: TOV2 (TC2 Over-flow flag), R.
(4) Summary of the working principle of Fig-10.3 and Fig-10.4
a. In Fig-10.4, waveform-4 shows the PWM signal whose period is T = 16 us and the corresponding frequency is 1/T = 62500 Hz = 62.5 kHz based on clkTC2 = 16 MHz.
b. PWM2A of Fig-10.3 is the "PWM Signal Generator for Channel-A". It becomes enabled when "Mode-3 Operation Mode" is selected by putting "0, 1, 1" into "WGM22, WGM21, WGM20" bits of TCCR2A and TCCR2B registers.
c. The PWM signal begins with HIGH level (non-inverting mode) and remains HIGH until the counts of TCNT2 arrives at point-Q (waveform-1 of Fig-10.4) where the contents of TCNT2 and OCR2A register are equal. The "electronics logic" of the "PWM Circuit" inside the MCU is arranged in such a way so that when the said equality happens, the logic level of PWM signal drops from HIGH-to-LOW. Here, we observe that by changing the content of OCR2A register, we can shift the position of point-Q and hence change the ON-time (duty cycle) of the PWM signal.
Let us choose clkTC2 (Fig-10.3) at 16 MHz with "TC2 Prescaler' set at /1 (divider 1).
(4) Initializing relevant registers to produce 62500 Hz (62.5 kHz) PWM signal at DPin-11 of Fig-10.3.
(a) Initially, the PWM signal (OC2A signal) at DPin-11 will be at HIGH level (non-inverting mode). When match occurs (contents of OCR2A and TCNT2 become equal), PWM signal will become LOW (OC2A signal is clear). PWM signal (OC2A signal) will assume HIGH level again when TCNT2 reaches at BOTTOM count (0x00) at point-R of Fig-10.4. All these events will happen when "1 and 0" are stored in "COM2A1 and COM2A0" bits of TCCR2A Register (Fig-10.5).
Figure-10.5: Bit layout of TCCR2A register
(b) It is desired that the ON-time (pulse width) of the PWM signal would be regulated by the content of OCR2A Register. The content of the OCR2A register is termed as the "TOP" value with which the content of TCNT2 would be continuously compared. When match occurs (contents of OCR2A and TCNT2 become equal), PWM signal will become LOW (OC2A signal is clear). PWM signal (OC2A signal) will assume HIGH level again when TCNT2 reaches at BOTTOM count (0x00) at point-R of Fig-10.4. This is known as Mode-3 Fast PWM mode operation to initialize which, the WGM bits (WGM22, WGM21, WGM20 = 0, 1, 1) of the TCCR2A (Fig-10.5) and TCCR2B (Fig-10.6) are used.
...to be continued