I need some help with changing the delay between the SDA and CLK in the I2C Communication!
Looking at the attached picture, Yellow is the CLK (A5) and Green is the SDA(A4) from the Arduino.
Currently the rising edge of the CLK is at the center of the data. Is it possible to change the timing between the CLK and SDA. For some reason we are not getting the ACK bit so we would like to play with this timing.
A slave can extend the SCL LOW time.
Thank you so much for the quick reply.
I am new to I2C Communication. Could you please elaborate on this.
Our DUT is an ASIC. We do the I2C communication for register read/writes.
Let the ASIC hold SCL low until it has processed or provided the current bit. In detail keep SCL low after the 8th bit until the SDA ACK level is stable.
The way we are doing the register read/write is as follows. First I upload the Standard Firmata and after that I use PYMATA library and use python 3.7 to do the register read/writes.
Could you please guide me which section of the Standard Firmata do i need to modify to keep the SCL low after the 8th bit.
Sorry, I have no idea of your development software. It's not an Arduino issue
Sure thank you so much for the help. Will try to understand the Standard Frimata and make the appropriate changes.
try decreasing the value of pull up resistors?
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