To elaborate a little more about changing DLYBCT, I've been able to communicate with SPI using 0 delay between transfers at a clock speed of 12 MHz and temporarily at 30 MHz, but my interconnect leads were too long to maintain 30 MHz reliably. A major difference with my testing is that I had the Due in SPI slave mode and directly utilized the SPI registers. The master (which controlled the SCLK rate) was an FTDI 2232H interface.
Note that Due's SPI can be set for 16 bit (maximum) transfer mode. When transferring more than 16 bits, there needs to be enough time to check the flags and read the Receive Data Register (a few MCLK cycles). This may limit the maximum SCLK rate for reliable transmission, but perhaps 21 MHz would work when the delay between transfers is set to 0.
The delay between transfers by default will put a 32 MCK gap between every transfer. It can only be changed in steps of 32 MCKs.
The drawback for large bit size continuous transfers is that low level programming using the SPI User Interface is required.