Cortex M0+ instruction set - why?

Projects Programming
1

Hi,
I note that one of the Cortex M0+ instruction set has an unusual property:

Unlike LSLS/LSRS/ASRS instructions that support either a 5-bit field (0-31) i.e.

LSRS Rd, #4

or

ASRS Rd, Rs

The RORS instruction only supports:

RORS Rd,Rs

What is more, the definition states:

Rd := Rd ROR Rs[7:0] * C flag unaffected if Rs[7:0] is 0.

So that means that the bottom byte (8 bits) of Rs defines the rotate value. Now I can only presume that there was a very good reason for this but I'm afraid I'm lost. It MAY be of use setting up a handful of 32-bit values into registers that is smaller than using a literal pool.

e.g

0000 0000 0010 0000b x 0000 0000 0010 0000b = 0000 0100 0000 0000

Not a huge boon for quickasm coders but if you happen to have inner-loops that would benefit, maybe it's the saving you need.

I need literally less than 50 instructions of code-fragment beneath which the entire project hangs so I was hoping someone else similarly struggling would find a use for it.

Cheers C

PS is the 64-bytes of cache on the Uno M0 memory mapped?

2

PS is the 64-bytes of cache on the Uno M0 memory mapped?

No, in fact how can it be? It is in the pipeline to the decode register. The whole point is that this memory doesn’t have to go through a fetch cycle.

Not sure what you are asking in the first part of the question. It can be useful to have instructions that do not set the flags so to preserve the state from a previous operation for branching on later. I know that is what I use them for.

3

The RORS instruction only supports: RORS Rd,Rs
What is more, the definition states: Rd := Rd ROR Rs[7:0] * C flag unaffected if Rs[7:0] is 0.

I don't understand which part you're complaining about. The lack of an immediate form? (that would make it a 32bit Thumb2 instruction, which M0 doesn't support.) The idea that the rotate amount can be larger than the word size? (seems to be generally true of the ARM shift instructions.). The "no condition codes if 0" part?
The M0 instruction set, in general, has some really annoying omissions...