I did some improvements there - I've put an internal oscillator (ring oscillator) in the CPLD, which runs at ~135.27MHz. There is an additional NSEL pin (selects internal/external oscillator as the source of the signal for the counter, you may gate the sources with NGATE) see below.
When running (atmega @ 16MHZ) and counter is sourced from internal oscillator and I gate it without a delay:
//gate the counter input
fastDigitalWrite(NGATE, LOW);
fastDigitalWrite(NGATE, HIGH);
//
I get CPLD counter= 17. So based on the internal oscillator frequency and counter value the delay between those two fastDigitalWrites measured is 125.67nSec. The internal CPLD ring osc. frequency has been measured with
//gate the counter input
fastDigitalWrite(NGATE, LOW);
delay(1000);
fastDigitalWrite(NGATE, HIGH);
//
and I read 135273234, stable on ~4-5 digits (the ring oscillator is temperature and voltage dependand).
P.
@Graynomad - Xilinx will send you a DVD with the latest development package free of charge, just do register and request it. I got it in a ~week in my post.
You need few GBytes free on your HDD, but frankly, when you understand digital the learning curve is steep as you need just learn few clicks with creating a project, select the device, then draw the schematics (like Eagle, but much simpler), assign the pins (few lines text file), synthetise/compile - one click), and flash (about 3-4 clicks). You need a programmer, I am using an LPT based one - 4diodes, 4resistors and 3V3 voltage reg.. and it works ! 
