DAC xtal bypass cap

Hi.

I want to make a shield with a dac and a 12.888MHz xtal. I saw that I have to put bypass cap on it, ut neither on dac or xtal data sheet I could find what value it should be...

Someone a a clue ?

Thank.

Nitrof

Please post a schematic so we know what DAC, xtal, and cap you're talking about.

I have not stop a final choice on the xtal, I check some datasheet of some at the right value, and they do not have any info on any of them.

For the dac, it is AD1934.

Not much info about that to.

On page 9, you have the pinout and pin function, i that case, MCLKI/XI and MCLKO/XO.

And on page 25, you have the filter to use when using an xtal.

But this pretty much what I've got.

[EDIT] I think a will take this xtal: LFXTAL003286

Which Arduinos are you supposing can drive this at full rate with 4 I2S streams?
I would imagine the standard sort of decoupling setup for I2S devices would apply to this chip too(*). It looks
pretty complex for a first foray into I2S audio signal conversion.

(*) 100nF each digital supply pin, 100nF + 10uF for every analog supply pin. Separate analog and digital
groundplanes, joined only under the chip. Back-to-back diode link between AVdd and Vdd to force the supplies
to come up together, separate linear regulator for 3.3V AVdd.

Basically the usual stuff for mixed signal.

Chips like this almost never specify swamping capacitor value for an external crystal because the value is dependent on the crystal characteristics, not the IC characteristics. Try 18pF.

OK thanks. MarkT, Lot of thing I did'n knew. Especially, add cap for all pin...

For the board, I will try first with DUE. I am not using all 8 output but only 4.
I'm trying to do a digital xover.

I found a library to filter that, as right now, DUE seem able to handle. ut it is not exclude to move to esp32...

I will use PDC adc, and I split negative and positive input into 2 ADC, to gave me 24 bit resolution with active rectifier.

I will apply all advise all gave me, this is what I add done so far:
Imgur

aarg, will go for that value.

Especially, add cap for all pin

That is not what he said, read it again.

I will use PDC adc, and I split negative and positive input into 2 ADC, to gave me 24 bit

Bad idea.
Anyway 12 bits resolution on each half of the cycle gives you 13 bits resolution not 24 bits.

That is not what he said, read it again.

I should have said: all supply pin...

Bad idea

I tough so, I make a simulation on ltspice, wave is correctly rectified, At eyes, I don't see deformation. but before going any further, I will test it on real to hear it at least once using DUE DAC.

gives you 13 bits

I feel so often dummy...

I'm stuck at home for some time, so I will continue a bit to develop the concept just for fun and to continue learning. With those advice, I don't thin this project will come to real one day...

On the subject of learning... this I don't understand what it could make electronically:

Back-to-back diode link between AVdd and Vdd to force the supplies
to come up together

The chip has a separate logic supply distribution and analog supply distribution on the metalization
layers, so that digital noise from the logic sections doesn't pollute the analog sections of the chip. True of
almost any ADC or DAC.

The interfaces between analog and digital generally assume both sections are powered together, so you can
ensure this with back-to-back diodes between the supply rails, so that they are never more than about 0.6V different. This still prevents noise from the logic supply getting onto the analog supply though, assuming you
use signal diodes with very low capacitance (1N4148 being the obvious choice), as once the voltage regulators
have both risen to 3.3V the diodes are off. This is possibly a paranoid precaution, but some chips give an absolute maximum difference between supplies or specify restrictions on power-up sequence.

Ok.

To be sure I understand well, those 2 diode have to be back in series between the 2 supply?
Not sure how to formulate my sentence; it use forward voltage and reverse leaking current?
Or are they simply in parallele ?

so that they are never more than about 0.6V different.

this should not be 1 if forward voltage of 1n4148 is 1v ?