Not sure if this should be on electronics or programming forum so apologise if I am in wrong place.
I am designing a board which has up to three X four channel DAC's and am using the LTC1664.
I notice from the datasheet http://cds.linear.com/docs/en/datasheet/1664fa.pdf that I can daisy-chain them by connecting the MISO of chip 1 to MOSI of chip 2 and by using the same chip select line for all DAC's.
What I can't work out from the datasheet is does this give me 12 individual channels (which is what I need) or 3 sets of 4 channels where channel 1 is set to the same output on all chips?
If its the former, then how do I address say channel 2 on chip 2 etc?
After a quick look it looks like the DAC's operate with a 16 bit system.
For each internal DAC, you supply 16 bits of data which includes the address of 1 of the 4 internal DAC's.
Once you clock 16 bits into the first chip, the next 16 bits clocked in apply to that first chip and the first 16 bits apply to the next chip in line. So you'd have to clock in 32 bits to control 2 chips.
The outputs will be independent, but you can only set one DAC at a time in each chip with every 32 bits. So you can only set 2 DAC's with 32 bits, but all 8 DAC outputs will be independent.
So say the address of the first chip DAC1 is 0001 and the address of DAC3 in the second chip is 0011, and you are setting them both to zero. The bits clocked in would have to be like this stream:
0011 (second chip DAC3)
000000000000 (setting, 10 bits plus 2 dont care bits)
0001 (first chip DAC1)
000000000000 (setting, 10 bits plus 2 dont care bits)
So the second chip data is sent first, then the first chip data.
I would guess that next you enable something to get the codes to become fixed until the next setting.
For four chips you'd have to clock in 64 bits starting with the last chip data and ending with the first chip data.
From this, I assume that if I have two chips, I will always have to send 32 bits, and from the data sheet, if I use an address of 0000 for the chip I don't want to set, it won't change.
I also assume that I set the CS line low and send ALL 32 bits before re-asserting it high (or 48 bits or 64 bits etc...)
I'm guessing that the chip has something like a 16bit FIFO register for the instruction coming in from the MOSI line and that the overflow is passed out the MISO to the next chip - makes sense now.