This got me thinking, is there a "too high" value of decoupling capacitor, if my time scale is not too small (0.1-1s) ? Is there any reason why people recommend certain size of decoupling capacitors for power lines or signal lines? How could I think about these in general?
There isn't (in theory) and there is (in practice).
The decoupling caps are there to provide instant "energy" to the chip - important when the chip is operating at high frequencies and the power supply wire presents itself as an inductor - which prevents the energy being delivered to the chip as quickly as could have hoped / demanded.
So in theory, the bigger a decoupling cap, the better off you are.
However, bigger caps tend to be electrolytic capacitors that have high ESR / ESL, making them slow in delivering such charges. Smaller caps tend to have lower esr/esl, and different caps (tantalum for example) tend to have lower esr as well.
So what you see in practice is a compromise: low value capacitors that hold adequate amount of charge and have low esr.
If the capacitor value is too high the the high frequency responce suffers. That is why you have to use both a small cap 10 to 100 nF in parallel with a big one 10 to 100uF.
If too high capacitance causes frequency responce to suffer, why would adding more capacitance helps?
It is for something else.