I don't quite understand your application, or how you expect the internal clocking to work, and I don't have any manchester-encoded devices lying around to test with, so I don't think I can help any more in that area.
I guess "long" means the data bit is different than the last bit, while "short" means it's the same.
Huh. I looked at some of the hardware circuits that are used actually seem to implement something like this.
There's a flip flop (holds "last bit") and an XOR gate (does conditional "invert") Sort of.
Interesting page (doesn't talk about SW, though): https://www.allaboutcircuits.com/technical-articles/how-to-decode-manchester-encoded-data-using-hardware/
How did you decide the OCRA and OCRB values - the 7 and 3 in first case and 127 and 63 in the second? Are there any calculations involved?
This I can answer...
The Timers have "prescalers" that determine their counting rate. clk/1, clk/8, clk/64 (and some more, slower ones.) (clk is the cpu clock rate: 16MHz.)
This will determine the resolution of the ICR/OCR values. WIth clk/64, each clock tick will be 1/250000 s long, and 125kHz would need to transition the output every clock, which I think is impractical. With clk/1, a 1/125k period needs 128 clocks for the full cycle, and a transition half-way through. Taking into account "starting at 0", that means the you need to count to 127, with a transition halfway there (63) The same applies to using the /8 prescaler:
Tclk = 16e6/8 = 2e6
OCRtop = 2e6/125e3 - 1 = 15 (Hmm. Did I say 7? oops; it looks like I though 1/16 was a prescaler option.)
OCRpwm = (2e6/125e3)/2 -1 = 7
There are complications I did not notice before: Timer0 and Timer1 apparently share the prescaler, and Timer0 has to operate with the 1/64 prescaler for millis() and etc to work right. And Timer2 apparently has some other possible prescaler options. (and also: if you're using this as a "sample clock" for your incoming manchester signal, you probably want it to be a much higher-frequency than the data frequency. The "clk" in the above hardware diagram is a "system" or synchonization clock that doesn't have anything to do with the data frequency. I think.