Distributed vs. Non-Distributed Capacitors and the LDO tunnel of death

My first basic question is regarding the best locations for storage capacitors on a board. I am not concerned with de-coupling caps (i.e. the common 0.1uF approach) for various IC's on the board, rather more about bulk storage. From the reading I have done, it would appear that storing these capacitors near the voltage regulator (the shorter the distance the better) is preferable to having them distributed across the board. On the other hand, I would think that having localized storage (near potential spike loads) would help voltage stability by minimizing the distance that the power has to travel to the point of use. Or should I not be concerned with this and just put the largest storage cap that may be needed near the LDO and call it a day? FWIW, the boards in question are pretty small (i.e. 10x10cm) and the power lines are generally 32 mils wide and usually form a grid across one side of the 2-sided board.

My second question regards the LDO tunnel of death, i.e. the areas of stability and instability that are a function of LDO design, ESR, and input/output capacitance. Depending on the LDO and the manufacturer, capacitances beyond the minimum indicated in the data sheet are encouraged as promoting stability. I also gather that some LDO designs (presumably older ones) need some ESR and hence need to rely on electrolytic or tantalum output capacitors for output smoothing, while other (newer?) designs have eliminated the need for ESR and rely on ceramic capacitors on the output stage instead. However, few manufacturers publish a graph that shows the allowable ESR vs. capacitance curves (aka the tunnel of death) and even when they do, these charts are usually limited to the recommended range of output caps, not for output caps that are larger than the minimum recommended by the data sheet. Usually, the best one can hope for is for LDO manufacturers to publish ESR and capacitance recommendations and little else.

FWIW, I like placing a relatively large capacitor on the output (i.e. 470uF) of my LDOs to minimize the potential for spikes and so on. However, a 470uF cap is well beyond the minimum output caps recommended (and in some cases discouraged) by LDO manufacturers. So what is the downside of a large tantalum or aluminum electrolytic capacitor on the output of an LDO? And how worried should I be if I place the recommended output cap in addition to this storage cap about ringing, etc.? Many thanks for any insights!

Constantin:
I also gather that some LDO designs (presumably older ones) need some ESR and hence need to rely on electrolytic or tantalum output capacitors for output smoothing, while other (newer?) designs have eliminated the need for ESR and rely on ceramic capacitors on the output stage instead.

You do need to watch the ESR requirements and what type of capacitor you are using. There are Aluminum and Tantalum available now with a conductive-polymer counter-electrode which gives them orders of magnitude less ESR than traditional wet-aluminum or MnO2 Tantalum.

I've seen many times where someone replaces an MnO2-Ta with a Polymer-Ta because of the reliability benefits, only to find the regulator goes unstable due to the ESR dropping from 1ohm to 10mOhm.

You also have to be careful when using high-C ceramics. Their voltage coefficient tends to be so strong you aren't getting anything near the expected capacitance anyway.

Constantin:
FWIW, I like placing a relatively large capacitor on the output (i.e. 470uF) of my LDOs to minimize the potential for spikes and so on.

Are you picking that value based on measurements and simulations? If not, you need to do so.

Constantin:
So what is the downside of a large tantalum or aluminum electrolytic capacitor on the output of an LDO?

Most regulators have some form of short circuit protection. This limits the practical capacitance that the regulator can charge, especially during startup. If the short-circuit protection gets tripped, the regulator may keep shutting itself down.

The LDO is analog, and the larger capacitor doesn't have to be very close to it.
However, it should not be too far, since the copper traces could pick up things or influences traces next to it.

With a switching DC/DC converter (6...18V -> 5V), I had to use at least 22uF at the output, or it didn't work at all.

But if the capacitor with the LDO is very large, and the input of the LDO is shorted to ground, the current could flow back, and damage the LDO.

I agree with James C4S, there is a very big difference between capacitors.

Constantin:
what is the downside of a large tantalum or aluminum electrolytic capacitor on the output of an LDO?

The downside is that tantalum and electrolytic capacitors have relatively slow response times and are almost useless for decoupling.

Raw capacity isn't everything. There's a reason people use ceramics for this.

See: http://www.atmel.com/Images/DOC0484.PDF

fungus:
The downside is that tantalum and electrolytic capacitors have relatively slow response times and are almost useless for decoupling.

This only applies to traditional Al and Ta (MnO2) caps.

Valve caps using a polymer counter-electrode are ideal for decoupling because they have ESRs as low (or lower) as ceramics AND have stable capacitance with applied voltage.

Thank you all.

James, I just looked at your site and I thought I’d amuse you with my toaster-based reflow oven. It uses the rocket scream shield and an dual-channel SCR for the fan and the quartz tubes. I put a heat sink on the back of the unit for the SCR, as the SCR is mounted on the inside, while the Arduino + shield are housed on the outside, inside a plastic enclosure that I salvaged from a dead Neuton lawn mover.

I modified the program to allow Pb- and Pb-less solder profile selection using one of the shield buttons. I also insulated the unit extensively with 2000*F insulation to limit the thermal mass as much as possible. The unit runs great and the boards come out great also. The only thing is that one has to baby-sit the process a bit, i.e. open the door at the end to ensure a quick but controlled descent from reflow to room temperature.

And yes, that is high-temp RTV holding appliance grade insulation to the glass window. A small window allows me to peek inside but it’s really only there to take pictures with.

photo.JPG

[quote author=James C4S link=topic=158391.msg1186143#msg1186143 date=1365090193]
You do need to watch the ESR requirements and what type of capacitor you are using. There are Aluminum and Tantalum available now with a conductive-polymer counter-electrode which gives them orders of magnitude less ESR than traditional wet-aluminum or MnO2 Tantalum.[/quote]
Very good point. It may make sense to move exclusively to 'ceramic-allowed' LDO's and then use the recommended ceramic capacitor to be sure and call it a day.

[quote author=James C4S link=topic=158391.msg1186143#msg1186143 date=1365090193]
You also have to be careful when using high-C ceramics. Their voltage coefficient tends to be so strong you aren't getting anything near the expected capacitance anyway. [/quote]
This is new to me, will have to research but thanks for pointing it out! On the other hand, if a OEM recommends a particular capacitance and a ceramic to be used, presumably that would be covered, or not?

[quote author=James C4S link=topic=158391.msg1186143#msg1186143 date=1365090193]
Are you picking that value based on measurements and simulations? If not, you need to do so.[/quote]
:roll_eyes: Um... no, not simulating enough, I guess. :blush: I suppose there are no rules of thumb, like 'don't bother more than doubling the recommended output capacitance unless...'

FWIW, I have yet to encounter a ringing LDO, or trip the auto-shutdown on a Vreg... but I also do not want to push my luck. Last but not least... on a small board, does it make much a difference where the storage caps are located? That is, other than the minimum for the LDO, close to the LDO...

Another thing to watch out for with large capacitors on the output of your regulator, is that the regulator can become reverse-biased (Vout > Vin) when the power is turned off, depending on the characteristics of whatever is providing Vin.

Good to know... thank you!

Constantin:

[quote author=James C4S link=topic=158391.msg1186143#msg1186143 date=1365090193]
You also have to be careful when using high-C ceramics. Their voltage coefficient tends to be so strong you aren't getting anything near the expected capacitance anyway.

This is new to me, will have to research but thanks for pointing it out! [/quote]
It is an (increasingly) known characteristic of barium titante based ceramics (X7R, X5R, Y5V, Z5U). As rated voltages go down, so does the dielectric thickness. Thinner dielectric means stronger voltage coefficients. Unfortunately there is no standard (outside of military parts) on what the maximum voltage coefficient can be. I've seen losses as high as 80% with full rated voltage at rated temperature.

Tools like KEMET's WebSPICE simulate capacitor characterstics with applied temperature and voltage, which helps to see how their parts will work.

*Disclaimer, I work for KEMET.

There was a recently publicized article on the de-rating thing. Um...

http://www.adafruit.com/blog/2012/12/16/ee-bookshelf-temperature-and-voltage-variation-of-ceramic-capacitors-or-why-your-4-7µf-capacitor-becomes-a-0-33µf-capacitor/