You are right, the break even point is (slightly) above 100mA, and with the thermal restrictions and precautions event this continuous current cannot be reached, for both chips. Thanks for your link to the power calculation, I was not fully aware of the consequences for the current of 8 drivers in a package.

But I miss one detail from the calculations, the difference between bipolar and FET transistors. FET resistance increases significantly with temperature, and the power consumption is P = I² *R. This means that a not so optimal FET will produce more heat, what increases its resistance, what again produces more heat…

When I looked at the worst case, of about 10 Ohm at 125°, the power dissipation per driver is almost the same (0.1W) for both chips at 100mA. When we also take into account a heat resistance of 90°/W for the TPIC, this will limit its total power dissipation to 0.9W, as opposed to 1.1W for the ULN.

Now the same power calculation for the TPIC as for the ULN in the link, please correct me if I’m wrong:

With a case temperature of 50°C, junction 125°C, and 90°/W the allowed total power is (125-50)/90=0.83W.

~~With Ron=10 Ohm we get I² = 0.083, I=0.29A total, 36mA per driver.~~

~~Even with Ron=5 Ohm we get I² = 0.166, I=0.41A total, 51mA per driver.~~

~~This were significantly less than the 0.71/8=88mA for the ULN at 50°C case temperature.~~

~~If I’m right, a continuous current of 8*100mA would cause a temperature difference of at least 290°C, with a required TPIC case temperature of -160°C ~~

Correction: Wrong resistance

The power **per transistor** can be 0.83/8 ~ 0.1W.

That’s 0.1A at 10 Ohm, 0.14A at 5 Ohm.

Sorry for the confusion