DS3232 + PLL for a more accurate clock?

Right now I am tinkering with my DCF77 project: http://blog.blinkenlight.net/2012/12/01/dcf77-project/. One of the things that I need for the later stages is an accurate local clock. As it turns out the crystal is sufficient but resonators are not. However the crystal is good for something as 30 ppm but better than 3 ppm is way out of reach. An obvious solution to this are the DS3232 RTC chips. And actually I do not really need this for my project.

However it started me wondering. How hard would it be to design a 16 MHz clock accurate to better than 3 ppm based on an DS3232 plus a phase locked loop? Although I understand the theory behind PLL I have absolutely no design experience with those. But I am pretty convinced that there are some forum members that have knowledge in this area. So I wonder if anyone has a hint which PLL chips / circuits would be suitable for such an undertaking. I also thought about using a 10 MHz OCXO plus PLL but I think this would consume way to much power.

Do you think it would be a good idea to base an Arduino lock on a DS3232 + PLL?

If yes: how should something like this be designed? Which circuit and which chips? If no: what would be a better way?

A TCXO ought to be good enough. (Temperature-compensated crystal oscillator)

For instance here's one that's +/- 2.5ppm (but 3.3V and surface-mount): http://uk.farnell.com/fox-electronics/fox924b-16-000/tcxo-16-0mhz-3-3v-smd/dp/2063959

Ah, I was not aware that TCXOs are so cheap by now. → Problem solved :slight_smile:

Do you think it would be a good idea to base an Arduino lock on a DS3232 + PLL?

It is fairly easy to do, but probably not worth it.

You need two things:

1) a temperature sensor: a diode work work. 2) a process to calibrate your temperature sensor and your crystal.

Essentially, you will measure the error terms of your crystal at different temperature points and correct the timing keeping.

The correction can be done in software, or in hardware: for example, you can replace one of the caps on the crystal with a varicap (or a reverse-biased diode), and use the arduino to output a "tuning" voltage on that varicap.

The DS3232 is temperature compensated. I only asked about how to setup a PLL notr about implementing my own TCXO. I will buy a cheap TXCO, add a buffer and drive the clock from it.

My original question is already answered as a TCXO is cheap and good enough for my purposes.

Out of curiosity I would still be interested to learn how a PLL setup would have been done. This is not for setting it up but just for satisfying my curiosity. Anyone here who can point me in the right direction?

how a PLL setup would have been done.

Depending on what you mean by PLL.

With a PLL oscillator / clock generator, you have to alter the dividers / multiplier combos, based on temperature, to correct the output.

You can also use the temperature information to tune a VCO, as I indicated earlier.

Either case, you have to know the crystal's error terms and you have to correct it somehow - much easier through the avr's software than via additional hardware.

I did not want to correct the crystal. I wanted to replace it. The idea would have been to have a 32768 Hz signal from the DS3232 (accurate to 2 ppm). Then to divide it by 32 to arrive at 1024 Hz. This should be phase locked to a signal that is divided by 5^6. Thus the PLL should output 16 Mhz +/- 2ppm. This would be fed to the AVR. The question was which kind of chip is advisable.

What you are trying to tell me is how to compensate a crystal oscillator for temperature. This is something I understand but did not ask for.

So again: which PLL chips would be suitable for my purposes and how would I set it up? And to make it absolutely clear: this is for learning not for anything else. As it was already suggested I will use a cheap TCXO and replace the crystal with the TCXO.

The flaw in replacing a 16 MHz resonator with a PLL controlled by a 32 KHz reference crystal is that the overall error would be the drift term of the 32KHz oscillator (Both aging and more immediate thermal) this term will determine the ultimate short and long term stability and as such would require a high stability crystal and oscillator. Much less expensive and a GREAT DEAL to use an off the TCXO and be done with it. There are no real advantages to PLL's for high stability low frequency PLL controlled fixed frequency discrete component clock generators for anything except a teaching tool. Speculating on how to build them reveals a lack of knowledge of current technology. At VHF and UHF and to millimeter wave frequencies things like NCO's or DDS technologies are used where accuracy and speed of change are most important and under those circumstances for a number of reasons are superior to PLL technology and frequently less expensive for the degree of stability available VS performance.

Bob

As I said several times: I will use a TCXO. To repeat it once again: I WILL USE A TCXO. This is what I repeated several times.

I still would like to learn how this would have been done with a PLL.

Speculating on how to build them reveals a lack of knowledge of current technology.

This is exactly my point. I am asking if someone would please point me in the direction of learning the state of the art use and circuits for PLL. Please do not tell that I am lacking knowledge in this area. This is what I meant with

Although I understand the theory behind PLL I have absolutely no design experience with those. But I am pretty convinced that there are some forum members that have knowledge in this area.

So if anyone wants to point me out that I am lacking knowledge of PLLs - fine. You prove that you can restate my question as an answer. However this does not help me anything at all. I already know this.

Back to my question: where would I start to read and which circuits would I use?

-Udo

P.S. As I mentioned several times by now I will stick toMarkT's advice and use a TCXO. No need to tell me over and over again!

You might like to look at the TI application note for the 74HC4046 PLL chip, http://www.ti.com/lit/an/scha003b/scha003b.pdf.

This short tutorial (9 pages) on the web explains some theory (starter) - http://www.radio-electronics.com/info/rf-technology-design/pll-synthesizers/loop-filter-design.php -

Big PDF's with lots of formulas (main dish) - http://www.delroy.com/PLL_dir/DL2007/PLL_tutorial_slides_July07.pdf - - http://cppsim.org/PLL_Lectures/digital_pll_cicc_tutorial_perrott.pdf -

hope this helps

Thanks!!! Finally someone who understood my question :slight_smile: