Due Pin Mapping, Function Table and Spreadsheet

Official Hardware Mega Due
1

I've created this as a detailed reference for a project I might start and thought this could be of help to others.

*** Pin Mapping pdf (Jan 15, 2014) ***
http://www.testcor.ca/pdf/Due%20Pin%20Mapping.pdf

*** UPDATED: Due Function Table (Jan 20, 2014)***
http://www.testcor.ca/pdf/Due%20Function%20Table.pdf

  • Enhanced cell colours
  • Non-applicable pin assignments are grayed out

*** UPDATED: Due Pin Mapping Spreadsheet (Jan 20, 2014)***
http://www.testcor.ca/pdf/Due%20Pin%20Mapping.xls

  • Added column for LFBGA pins on second sheet
2

Yes, handy indeed.

Can you generate a re-ordered version that's ordered by PIO channel and bit number?
Sometimes that's useful if you want to choose a group of pins to drive
synchronously at a low level.

3

MarkT:
Can you generate a re-ordered version that's ordered by PIO channel and bit number?
Sometimes that's useful if you want to choose a group of pins to drive
synchronously at a low level.

Hello Mark,
Here's the original spreadsheet which will allow for various sorting methods, editing, cut/paste etc.
http://www.testcor.ca/pdf/Due%20Pin%20Mapping.xls

4

Nice tables, saved for future use.

Rob

5

Added Due Function Table.
http://www.testcor.ca/pdf/Due%20Function%20Table.pdf

6

Downloaded, thanks.

7

Tables updated again.

NOTE:
It seems there is an error in the SAM3X datasheet with labelling PA17 functions...

Table 11-2, Page 50:
I/O Line    Peripheral A    Peripheral B
PA17	         TWD0             SPCK0  <--- should be "SCK0" (for USART0)

Table 36-3, Page 780:
PA17	                          SCK0   <--- correct
8

So SPCK0 is for the SPI port, that's a gotcha.

Rob

9

New updates (see above).