DUE schmitt debouncer, understand timing cacul

Official Hardware Mega Due
1

Hi.

I want to use DUE debouncer.

I found all register involve and read this topic:

topic=138887.0

The part I do not understand is the formula to get the debounce time:

Tdiv_slclk = ((DIV+1)*2)*Tslow_clock
For the debouncing filter, the Period of the Divided Slow Clock is performed by writing in the DIV field of the
PIO_SCDR (Slow Clock Divider Register)

slow clock to be 32 768Hz, DIV, if I understant is 0 to 13. That as far as I can get.. what represent each variable? All thing I tried don't makke sens....

Thanks.
Nitrof

2

Digging, I think I got the answer.

It wasn't clear if DIV was mas or integral value.

I found in component_pio.h:

#define PIO_SCDR_DIV_Pos 0
#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing 
#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))

So, there, I understand that SCDR return an integral value, And I chec it can so.

Tslow_clock is the period of slow_clock that is set to 32768Hz datasheet p521 .

SCDR goes 0 to 16383 so debounce period =:

Tdiv_slclk Min = (0+1) *2 *(1/32768)  = 61ms
Tdiv_slclk Max = (8191+1)*2*(1/32768) = 500ms

seem to make sens...

Regards.

Nitrof