Due VDDPLL LC circuitry, what is its purpose?

Official Hardware Mega Due
1

Hello everyone,

I'm new to Arduino, but not to embedded systems.

I've built a device around an Arduino Due, and now I'm planning to make a single PCB out of my collection of breadboards and jumper wires.

I am comparing the Arduino Due schematic to the documentation for the Atmel SAM3X / SAM3A Series chips.

On the Arduino Due board, VDDOUT and VDDPLL are separated by an LC network which looks like it might provide low-pass filtering and power decoupling.

In the Atmel documentation, none of the power configuration diagrams look like this. The first schematic is Figure 5-2, but there are many others which describe alternate power configurations. In every case, VDDPLL is tied directly to VDDOUT.

What is the reason that the Arduino Due has this extra circuitry? I am guessing that it reduces ripple on VDDOUT, but Atmel doesn't think this is necessary. VDDOUT meets the ripple specifications for VDDPLL, at least nominally.

Are there certain optional, demanding applications which require extra ripple reduction on VDDPLL, and which Arduino was designed to accommodate? I'm thinking USB timing might be such an application. However, my device won't be connected to USB.

Thanks for any information you may have.

2

I would say that is correct.

Just because something is not shown on a data sheet does not mean it is not needed. In most data sheets there are normally some words to the effect you might need extra or more decoupling to achieve stable operation. My guess is that the developers of the Due were getting a bit of jitter on the PLL and so added this extra decoupling. Or maybe they had previous experience of designing with PLL and last time they solved the problem with extra decoupling so they used it in this project.

Its not a big issue and it only cost pence to fit so go with it.