This is easy. The intent is to ensure that the flash ADC decodes the correct address for each input voltage. Intuitively, that happens most securely when each input voltage is smack in the middle of the range that yields the corresponding code, except at the endpoints - a 0V input will give a 0 reading from the flash ADC, and VDD will always give a reading of 7, without any concerns about voltage errors.
The bottom of the range for each code is ADDR * VDD / 8, the top is (ADDR + 1) * VDD / 8, so the middle is (2 * ADDR + 1) * VDD / 16. Those values match Figure 1-3 perfectly. It takes 7 resistors: one with a value of 3R, followed by five at 2R, and another at 3R, where R is some convenient value, to get 0V at one end, VDD at the other, and an exact match with Figure 1-3 at the junctions in between.