Faster Routine

An example of SPI_CSR programming:

// Data transfer parameters
SPI0->SPI_CSR[0] = SPI_CSR_CPOL          // Inactive state value of SPCK is logic level one
                    | SPI_CSR_NCPHA       // Data is captured on the leading edge of SPCK and changed on the following edge
                    | SPI_CSR_CSNAAT       // Chip select active after transfer
                    | SPI_CSR_BITS_12_BIT // Bits per transfer
                    | SPI_CSR_SCBR(100)   // bit rate
                    | SPI_CSR_DLYBS(100); // delay from NPCS falling edge (activation)