FIFO Buffer

Hi All,

I am trying to read data at 1 Mhz but process later at a slower pace. Ideally, I would like to find a component like a large FIFO that can ingest data at 1 Mhz and then output at a slower pace for example 100 Khz per byte. I did some googling it seems like a clock domain crossing problem. However, I am not an electronics expert and I was wondering if anyone would like to propose a chip that is very cheap that is capable of doing this. I dont want to use SRAM as I dont have sufficient IO pins. Also I am reluctant to use a chip that costs more than 5$ a piece.

Conceptually, I think of this chip as a FIFO that has two clock inputs, one for writing and one for reading. The write clock can be a fast one like 1 Mhz and the read one can be a slow one like 1 Khz or some sort of setting that allows the same clock at different frequency to be used. The FIFO I have now is AL422B, but it has a minimum refresh fequency of 1 Mhz and I am looking for something that can cope with a slower clock for reading or has a lower frequency refresh cycle. Perhaps and more non-volatile nature of FIFO that does not need a refresh might also work.

Thanks for reading my message and hopefully I can find a suitable chip.

What architecture?
SMD or thruhole?
http://www.digikey.com/product-search/en/integrated-circuits-ics/logic-fifos-memory/2556319?k=fifo

I dont understand what the question about architecture means. Do you mean sync or async ?

I was looking for a DIP package.

http//www.digikey.com/product-search/en/integrated-circuits-ics/logic-fifos-memory/2556319?k=fifo
Forum is messing up links, you may have to edit beginning & ending of that
Pan right, select thru hole, then pan back left and select Instock, and Apply Filter,
Cuts the list down quite a bit.

Also I am reluctant to use a chip that costs more than 5$ a piece.

Then I would suggest you find another project.

How big does this FIFO have to be?
How wide is this data?