I added FPGA.digitalwrites with no delays to the VidorTestSketch loop to see how fast the FPGA can toggle it’s pins and got 675Hz on my scope. Somewhat short of the 150Mhz stated on the store page. I am sure it can do this but how to get it to do so is the question.

Is this because the SAMD21 is telling the FPGA to do this every loop? I put in a two delay(1) and it goes to 500hz as expected.

Any ideas?

ARM uses JTAG to command FPGA to change IO state through mailbox.

For full IO switch rate you need your own custom IP. There are few limitations like JTAG for communication between ARM and JTAG is 12 MHz. So maximum speed is 12 Mbit/s in bursts.

You can create patterngenerator like 1024x8 and it repeats that area. With that you can drive IO for 150 MHz speed. You need configure PLL to ouput 300 MHz clock for that IP. (need to check if that 150 MHz is IO togglerate or fmax for IO)

For longer sequences you can use delay values for IO change. Like bit 7 = output value, bit 6-0 = delay value for change.

Ok. Looks like I have a lot of learning to do.

Do you know what would be good starting place to learn FPGA programming? A good website, book or course?

I have done fairly well on my own for the SAMD processors by just looking at all of the git repositories and matching them up to the datasheets. I don't know where to start for a FPGA. I definitely would like to learn how to build custom IP. Just would like to get off on the right foot.

Free web lessons for FPGA development from Intel.

Usefull sites:

I think they should make sticky thread with usefull links for FPGA development.