FPGA integrator

Dear Forum,
I have been using Arduino's for a while but just stepping into the world of FPGA. I would like to build a device that integrates a voltage over a period determined by a gated pulse. The gate could be externally provided or better provided by the FPGA device. It needs to be able to sample at 1 MHz on two separate channels. I am hopeful that the MKRVIDOR4000 will allow me to do this.

Can anyone point me towards tutorials or projects that would get me started on this project.
Thank you,

Hi Nick,
actually Vidor's analog capabilities are limited to what the Cortex M0 can do as FPGA does not have analog inputs.
what you want can probably be done with a microcontroller without the FPGA. SAM D21 on any MKR board can sample up to 1MHz and if you add a check on a pin in the interrupt for the ADC you have it done...
hope this helps...

Hello Dario,
Thank you very much for your response. I am not familiar with the MKR boards but have read a little and understand that it is possible to read an analog input at 1 MHz. I found a useful tutorial on you tube that goes through how to achieve this. Is there only one input on Arduino MKR boards? I read that some DAMD21 chips have multiple inputs. Can these be accessed at the same rate as I would ideally like to sampel at 1 MHz on two channels? I could just about get away with a 5us sample interval per channel. With other NI DAQ boards that I use, the more inputs accessed, the lower the overall possible speed as the fastest speed is divided down per input.

I also wonder if this method you suggest could give me a live output? Whilst it may sound odd, I would send the integrated output to a DAQ board. The reason is because I have already written lots of software using this hardware but the one thing I lack is the ability to integrate a signal over a defined period.


SAMD21 (Cortex M0+) datasheets tells that it's only 350 ksps for DAC and ADC. I think Cortex M3/4 had 1Msps converters.

But if 175ksps (interleaved sampling) is enough then you can try to use DMA. how many samples you are planning to use calculation?

Hi, datasheet says it's 350kbps for DAC. for ADC there's no figure because the frequency changes depending on averaging, prescaing etc and it can be set to high frequencies, even over a MSPS however this likely will result in samples with a low ENOB.
since the chip has just one ADC with an analog mux in front of it, you will have to divide the sampling frequency among channels and it will also introduce distortions given by the fact that ADC needs to "wait" for switch to be effective so in the end i am afraid that with multiple channels you won't go that far.
it sounds a bit strange to me you can't do some math using NI stuff... anyway yes, you can have a live output but you have to find out how to have that. 1MSPS is quite a lot and i don't see on which interface you could export all that data (assuming 10 bits per sample it's 10 mbit!). you may output that with a sigma delta DAC implemented in the FPGA but not sure this is what you want.

It seems fmax system clock for ADC is 2.1 MHz in family datasheet chapter 37.11.4.
When using 12 bit conversion (6 clk) it's 350 ksps. You can try to use 8 bit then it should be little over 500 ksps if sampling circuit is fast enough. I think you can change mux when doing conversion.

I think easiest to do multichannel capture is to use input mux scanning feature and DMA. Not sure do we need to restart scan or does it to restart automatically.

Datasheet of SAMD21

For my experiement 72MHz Cortex M3 was too slow to move data to ADC in interrupt for 1 Msps. I had to use DMA controlled from timer.