I would try to use OC1B as output and OCR1A as TOP for the Timer1. Since output compare registers are buffered and update only at safe part of the cycle there is no risk of the "missed TOP" glitch.
I would try to use OC1B as output and OCR1A as TOP for the Timer1. Since output compare registers are buffered and update only at safe part of the cycle there is no risk of the "missed TOP" glitch.