By the way, could you explain why a horizontol line that is drawn from left to the right is not complete
Hi Hulk, I missed that question you posted a while ago, and only just noticed it now.
I looks like its due to time it takes the panel to switch chips. I can reproduce it here and am looking at it in conjunction with the a solution for adjusting for the different delays required for different panels without having to throttle back the faster panels.
I would be interested in hearing how you guys think support for panels that required different delays should be handled
- slow down the library to the lowest common denominator
- provide a fast and slow compile time option
- provide some tuning advice and let each user tweek his panel to find the best response
- something else?