I'm trying to get reliable high-precision timing data of two separate (ideally, three or more) digital pulses on the rising edge. I tried doing this using external interrupts and capturing the time using a high precision routine found elsewhere on this forum that captures Timer0 ticks. The smallest difference between pulses arriving simultaneously appears to be 26 ticks, or 104 us. Is this because of the overhead of handling the ISR itself? If I need more precision, what's a better way of doing this? I was hoping to avoid having to use a high frequency timer interrupt so as to give some CPU time to the main loop, but I may have to go that route.
How precise of a measurement do you need?
I would use individual logic ICs or an FPGA.
For two signals I would use a counter and start it on one signal and stop
it on the second signal. The time value is the count / freq.
For more than two signals I would store the count into an SRAM each time
an edge occurs. Each edge would change the SRAM address and then latch
the count.
(* jcl *)