When reading about some HW features I often see things like L3 interconnect, L2 Cache master. Can someone explain what these layers mean? How many are there?
It's all about how the internals of a CPU communicate both with each other and the outside world.
In the old single core CPUs it was simple - you had a couple of layers of cache.
Think of the cache as a series of buckets. The data and code is stored in memory - in the "well outside". Instead of going to the well for every sip of water you want, you go and fill a bucket from the well. This sits in the kitchen (Level 2 cache). Then when you want a drink you go and fill a cup from the bucket - much faster than going out to the well. The cup is the L1 cache - smaller, but you can reach it from the comfort of the armchair.
Now with multi-core CPUs there has to be a way for each of the cores (houses surrounding the courtyard with the well in it) to use the well without them all arguing over who uses it when. The interconnect acts like a person by the well who you give your bucket to, who then gets the water from the well for you. If someone has brought back a bucket of water to go back into the well, and the water you want happens to be in their bucket, the interconnect will just give you that bucket instead of pouring the water back in the well, then dipping your bucket into the well to pull the water out again. This is the Level 3 interconnect cache.
Remember that on fast processors the cores run about 50 times faster than they can talk to the outside world,
and that signals take many clock cycles to cross from one part of the chip die to another - a cache on the opposite
side of the chip is inevitably an order of magnitude slower to access than the level 1 cache right next the core.
Modern gates have sub-picosecond response times and internal clocking zones might be 50GHz or more IIRC, meaning
that the zone cannot be more than about 0.3mm across to keep clock-skew under control. Modern VLSI design
is astonishingly complex in order to get the most from the silicon. Typically a chip will have a hierarchy of zones and
each will have its own clock-generation and power-reduction management strategy. Its common now to dynamically
adjust supply voltage and clock speed to parts of a processor.
Faster level 1 caches are static RAM (more area and power hungry), whereas DRAM might be employed for the
larger level 3 cache to save power and chip area.
This complexity isn't present in low-power low-speed chips like simple microcontrollers, we're talking proper CPUs...
Learn something new everyday.
Thanks guys. +1