Help with Timer Input Capture / receiving data for bit banging.

Hello everyone,

I have been struggling for awhile with the software for a protocol that I'm trying to bit bang. I can send data just fine and it works great. I just can not get a proper software solution that's reliable for receiving data off of the bus.

I have tried multiple different attempts and all partially work. The issue I am running into is that the data on the bus is drifting. The timing is suppose to be 100us bit width per the standards of the protocol but when you actually start working with it you will find it drifts way out of those specs.

For instance
First SOF High bit is 112us
Next Low bit 116us
Next Two low bits total will be 230us (115us each)
Next 3 High bits total will be 300us (100us each).
Next High bit 116us

See how the timings are really loose and not consistent so all my attempts to bit bang it work but my timing is so precise that I end up getting garbage after the first 6 bytes or so as the timing is out of sync.

I have decided to attempt to use Timer1 Input Capture to determine the time width of each bit and then divided that time by 100us (the base time of the protocol) this should allow me to read bits accurately even if the timing is off by a small amount. Then I can shift each bit into a byte one at a time.

I have started learning how to use the Timer1 Input capture ISR but I am having issues. Every thing I read tutorial wise is about how to measure length of pulses that are high and ignoring low state timing.

I need to be able to measure the time of low state and high state since I am dealing with logic and bits not PMW or Duty Cycles.

Is anyone willing to throw me a bone and help me out. It's been a long few weeks since everything I try ends up at a dead end because of this timing drift issue. This looks to be the exact solution I'm looking for.

Thank you,

I would not use timer input capture for such low speed - 100 usec. Attachinterrupt() would be sufficient to time-stamp rising / falling pulse transition